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参数资料
| 型号： | M7010R-083ZA1T |
| 厂商： | 意法半导体 |
| 英文描述： | 16K x 68-bit Entry NETWORK SEARCH ENGINE |
| 中文描述： | 16K的× 68位进入网络搜索引擎 |
| 文件页数： | 42/67页 |
| 文件大小： | 449K |
| 代理商： | M7010R-083ZA1T |
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M7010R
42/67
272-bit Configuration
Figure 31, page 43 shows the timing diagrams for
a SEARCH operation in the 272-bit-configured ta-
ble (CFG = 10101010) consisting of a single de-
vice for one set of parameters: TLSZ = 00, HLAT
= 001, LRAM = 1, and LDEV = 1. The hardware di-
agram for this search subsystem is shown in Fig-
ure 30.
–
Cycle A:
The host ASIC drives the CMDV high
and applies the SEARCH command code (10)
to CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair for bits
[271:136] of the data being searched. DQ[67:0]
must be driven with the 68-bit data ([271:204])
to be compared to all locations
“
0
”
in the four 68-
bits-word page. The CMD[2] signal must be
driven to logic '1.'
Note:
CMD[2] = 1 signals that the search is a
x272-bit search. CMD[8:3] is ignored.
–
Cycle B:
The host ASIC continues to drive
CMDV high and continues to apply SEARCH
command
code
(10)
DQ[67:0] is driven with 68-bit data ([203:136]) to
be compared to all locations
“
1
”
in the 68-bits-
word page.
–
Cycle C:
The host ASIC drives the CMDV high
and applies the SEARCH command code (10)
to CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair for bits
[135:0] of the data being searched. CMD[8:6]
signals must be driven with the bits that will be
driven on SADR[21:19] by this device if it has a
hit. DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared to all locations
“
2
”
in
the four 68-bits-word page. The CMD[2] signal
must be driven to logic '0.'
–
Cycle D:
The host ASIC continues to drive
CMDV high and applies SEARCH command
on
CMD[1:0].
The
code (10) on CMD[1:0]. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and hit flag (see Table 9, page 19 for a de-
scription of SSR[0:7]). The DQ[67:0] is driven
with the 68-bit data ([67:0]) to be compared to all
locations
“
3
”
in the four 68-bits-word page.
CMD[5:2] is ignored because the LEARN In-
struction is not supported for x272 tables.
Note:
For 272-bit searches, the host ASIC must
supply four distinct 68-bit data words on
DQ[67:0] during Cycles A, B, C, and D. The
GMR Index in Cycle A selects a pair of GMRs
that apply to DQ data in Cycles A and B. The
GMR Index in Cycle C selects a pair of GMRs
that apply to DQ data in Cycles C and D.
The SEARCH command is a pipelined operation
that executes searches at one-fourth the rate of
the frequency of CLK2X for 272-bit searches in
x272-bit-configured tables. The latency of SADR,
CE_L, ALE_L, WE_L, SSV, and SSF from the
272-bit SEARCH command (measured in CLK cy-
cles) from the CLK2X cycle that contains the C
and D cycles is shown in Table 33, page 44.
The timing diagram for all SRAM interface signals,
SSV, and SSF shift to the right for different values
of TLSZ, as specified in Table 31, page 44.
In addition, SSV and SSF shift to the right for dif-
ferent values of HLAT, as specified in Table 32,
page 44.
In the 272-bit configuration, SEARCH takes two
CLK cycles. The result of the SEARCH operation
appears as an SRAM READ Cycle with a pipelined
latency measured from the second cycle of the
command, as specified in Table 33, page 44.
Figure 30. Hardware Diagram for a Table with One Device (272-bit Operation)
DQ[67:0]
CMDV, CMD[8:0]
SSF, SSV
SRAM
LHO[1]
BHI[2:0]
BHI[2:0]
LHI
3
2
1
0
M7010R
LHO[0]
6
5
4
AI07040
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