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参数资料
| 型号： | M72DW64000B90ZT |
| 厂商： | 意法半导体 |
| 英文描述： | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product |
| 中文描述： | 64兆比特（x8 / x16插槽，多银行，引导块）和16Mbit的闪存伪静态存储器，3V电源，多记忆体产品 |
| 文件页数： | 7/19页 |
| 文件大小： | 102K |
| 代理商： | M72DW64000B90ZT |
7/19
M72DW64000B
t
RHEL
,
M29DW640D datasheet for more details.
Holding RP
F
at V
ID
will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
erations Ready/Busy is Low, V
OL
. Ready/Busy is
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE).
The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
lect is Low, V
IL
, the Flash memory is in x8 mode,
when it is High, V
IH
, the Flash memory is in x16
mode.
PSRAM Chip Enable inputs (E1
P
, E2
P
).
The
Chip Enable inputs activate the PSRAM control
logic, input buffers and decoders. E1
P
at V
IH
with
E2
P
at V
IH
deselects the memory, reducing the
power consumption to the standby level, whereas
E2
P
at V
IL
deselects the memory and reduces the
power consumption to the Power-down level, re-
whichever
occurs
last.
See
the
gardless of the level of E1
P
. E1
P
and E2
P
can also
be used to control writing to the PSRAM memory
array, while W
P
remains at V
IL.
It is not allowed to
set E
F1
at V
IL,
E1
P
at V
IL
and E2
P
at V
IH
at the
same time.
PSRAM Upper Byte Enable (UB
P
).
The Upper
Byte Enable input enables the upper byte for
PSRAM (DQ8-DQ15). UB
P
is active low.
PSRAM Lower Byte Enable (LB
P
).
The Lower
Byte Enable input enables the lower byte for
PSRAM (DQ0-DQ7). LB
P
is active low.
V
CCF
Supply Voltage (2.7 to 3.3V).
V
CCF
vides the power supply for Flash memory opera-
tions (Read, Program and Erase).
The Command Interface is disabled when the
V
CCF
Supply Voltage is less than the Lockout Volt-
age, V
LKO
. This prevents Bus Write operations
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1μF capacitor should be connected between
the V
CCF
Supply Voltage pin and the V
SS
Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I
CC3
.
V
CCP
Supply Voltage (2.7 to 3.3V).
V
CCP
pro-
vides the power supply for
the PSRAM.
V
SS
Ground.
V
SS
is the ground reference for all
voltage measurements in the Flash and PSRAM
chips.
pro-
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