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参数资料
| 型号： | M7705 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分类： | Codec |
| 英文描述： | 4ch Single Rail CODEC |
| 中文描述： | 4路单铁编解码器 |
| 文件页数： | 5/20页 |
| 文件大小： | 144K |
| 代理商： | M7705 |
Semiconductor
MSM7705-01/02/03
5/20
DIN1, DIN2, DIN3
PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected.
D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals
synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are
output from AOUT1, AOUT2, and AOUT3 pins, respectively.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).
DIN4
PCM signal input for channel 4 when the parallel mode is selected.
D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous
with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4
pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input.
BCLK
Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4.
The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit
and receive circuits to the power saving state.
RSYNC
Receive synchronizing signal input.
Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3,
and DIN4 pins by the receive synchronizing signal.
All timing signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same clock source as
BCLK). The frequency should be 8 kHz
±
50 ppm to guarantee the AC characteristics which are
mainly the frequency characteristics of the receive section.
However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics
of the system used are strictly specified, but the electrical characteristics specified in the data
sheet are not guaranteed.
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