参数资料
型号: M8803F3Y-90T1T
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封装: PLASTIC, QFP-52
文件页数: 4/85页
文件大小: 601K
代理商: M8803F3Y-90T1T
M88 FAMILY
12/85
in CSIOP space. The following section gives a
more detailed description.
M88 FAMILY FUNCTIONAL BLOCKS
As shown in Figure 3, the M88x3Fxx FLASH+PSD
consists of six major types of functional blocks:
t Memory Blocks
t PLD Blocks
t Bus Interface
t I/O Ports
t Power Management Unit
t JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
Memory Blocks
The M88x3Fxx FLASH+PSD has the following
memory blocks:
– The main Flash memory
– Optional secondary EEPROM or Flash boot
memory
– Optional SRAM.
The memory select signals for these blocks
originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft.
Table 10 summarizes which versions of the
M88x3Fxx FLASH+PSD contain which memory
blocks.
Main Flash and Optional Secondary EEPROM
or Flash Boot Memory Descriptio n
The 1 Mbit main Flash memory block is divided
evenly into eight 16 KByte sectors. The optional
EEPROM or Flash Boot memory is divided into
four sectors of 8 KBytes each. Each sector of
either memory can be separately protected from
program and erase operations.
Flash memory may be erased on a sector-by-
sector basis and programmed byte-by-byte. Flash
sector erasure may be suspended while data is
read from other sectors of memory and then
resumed after reading.
EEPROM may be programmed byte-by-byte or
sector-by-sector, and erasing is automatic and
transparent. The integrity of the data can be
secured with the help of Software Data Protection
(SDP). Any write operation to the EEPROM is
inhibited during the first five milliseconds following
power-up.
During a program or erase of Flash, or during a
write of the EEPROM, the status can be output on
the Ready/Busy pin of Port C3. This pin is set up
using PSDsoft Configuration.
Memory Block Selects
The decode PLD in the M88x3Fxx FLASH+PSD
generates the chip selects for all the internal
memory blocks (refer to the section entitled
“Decode PLD (DPLD)”, on page 25). Each of the
eight Flash memory sectors have a Flash Select
signal (FS0-FS7) which can contain up to three
product terms. Each of the optional four EEPROM
or Flash Boot memory sectors have a Select
signal (EES0-3 or CSBOOT0-3) which can contain
up to three product terms. Having three product
terms for each sector select signal allows a given
sector to be mapped in different areas of system
memory. When using a microcontroller with
separate Program and Data space, these flexible
select signals
allow dynamic re-mapping of
sectors from one space to the other.
The Ready/Busy Pin (PC3)
Pin PC3 can be used to output the Ready/Busy
status of the M88x3Fxx FLASH+PSD. The output
on the pin will be a ‘0’ (Busy) when Flash or
EEPROM memory blocks are being written to, or
when the Flash memory block is being erased.
The output will be a ‘1’ (Ready) when no write or
erase operation is in progress.
Memory Operation
The main Flash and optional EEPROM or Flash
Boot
memories are
addressed
through
the
microcontroller
interface
on
the
M88x3Fxx
FLASH+PSD device. The microcontroller can
access these memories in one of two ways:
t The microcontroller can execute a typical bus
write or read operation just as it would if
accessing a RAM or ROM device using standard
bus cycles.
t The microcontroller can execute a specific
instruction that consists of several write and read
operations. This involves writing specific data
patterns to special addresses within the Flash or
EEPROM to invoke an embedded algorithm.
These instructions are summarized in Table 11.
Typically, Flash memory can be read by the
microcontroller using read operations, just as it
Table 10. Memory Blocks
Device
128
KByte
Main
Flash
32 KByte
EEPROM
32 KByte
Boot
Flash
2 KByte
SRAM
M8813F1x
Yes
No
Yes
M8803F2x
Yes
No
Yes
No
M8813F2x
Yes
No
Yes
M8803F3x
Yes
No
M8813F3x
Yes
No
Yes
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