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参数资料
| 型号： | M88 |
| 厂商： | 意法半导体 |
| 英文描述： | In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| 中文描述： | 在系统可编程ISP的多内存和CPLD的逻辑FLASHPSD系统的微控制器 |
| 文件页数： | 5/7页 |
| 文件大小： | 67K |
| 代理商： | M88 |
5/7
M88 FAMILY
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial
interface allows complete programming of the
entire FLASH+PSD device. A blank devicecan be
completely programmed for the first time after it is
soldered to the board. The JTAG signals (TMS,
TCK,
TSTAT,
TERR,
multiplexed with other functions on Port C. Table 4
indicates the JTAG pin assignments. Four-pin
JTAG is also fully supported.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire
FLASH+PSD device can be programmed or
erased without the use of the MCU. The primary
Flash memory can also beprogrammed in-system
by
the
MCU
executing
algorithms out of the secondary memory, or
SRAM.
The
secondary
programmed thesame way by executing out of the
primary
Flash
memory. The
FLASH+PSD
Configuration
programmed through the JTAG port or a device
insertion programmer. Table 5 indicates which
programming methods can program different
functional blocks of the FLASH+PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user controlof the power consumptionon selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The FLASH+PSD also has some bits that are
configured at run-time by the MCU to reduce
TDI,
TDO)
can
be
the
programming
memory
can
be
PLD
blocks
or
can
other
be
power consumption of the CPLD. The Turbo bit in
the PMMR0 register can be reset to 0 and the
CPLD latches its outputs and goes to sleep until
the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. Please see
the full data sheet for more details.
SECURITY AND NVM SECTOR PROTECTION
A security bit in the Protection Register enables
the software project, coded in the FLASH+PSD, to
be locked up. This bit is only accessible by the
system designer fromthe JTAG serial port, or from
a parallel insertion programmer. It cannot be
accessed from the MCU. The only way a security
bit can be cleared is to erase the entirechip.
The contents of the sectors of the primary and
secondary NVM blocks can beprotected using bits
in the Protection Registers. These bits are
accessible from the MCU in the application code,
or
from
a
programmer
procedure.
during
the
set-up
Table 3. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD)
73
17
42
Complex PLD (CPLD)
73
19
140
Table 4. JTAG SIgnals on Port C
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Table 5. Methods of Programming Different Functional Blocks of the FLASH+PSD
Functional Block
JTAG Programming
Device Programmer
IAP
Primary Flash Memory
Yes
Yes
Yes
Secondary EEPROM or Flash memory
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
FLASH+PSD Configuration
Yes
Yes
No
OTP Row
No
Yes
Yes
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