- 您现在的位置：买卖IC网 > PDF目录262949 > M95010-WDW3TR (STMICROELECTRONICS) 128 X 8 SPI BUS SERIAL EEPROM, PDSO8 PDF资料下载
参数资料
| 型号： | M95010-WDW3TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 128 X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, TSSOP-8 |
| 文件页数： | 9/37页 |
| 文件大小： | 586K |
| 代理商： | M95010-WDW3TR |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
17/37
M95040, M95020, M95010
Write to Memory Array (WRITE)
As shown in Figure 13., to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High after the rising edge of Serial Clock
(C) that latches the last data bit, and before the
next rising edge of Serial Clock (C) occurs any-
where on the bus. In the case of Figure 13., this
occurs after the eighth bit of the data byte has
been latched in, indicating that the instruction is
being used to write a single byte. The self-timed
Write cycle starts, and continues for a period tWC
(as specified in Table 18. to Table 22.), at the end
of which the Write in Progress (WIP) bit is reset to
0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 14., the next byte of input
data is shifted in. In this way, all the bytes from the
given address to the end of the same page can be
programmed in a single instruction.
If Chip Select (S) still continues to be driven Low,
the next byte of input data is shifted in, and is used
to overwrite the byte at the start of the current
page.
The instruction is not accepted, and is not execut-
ed, under the following conditions:
–
if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)
–
if a Write cycle is already in progress
–
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock
(C) that latches the last data bit, and before
the next rising edge of Serial Clock (C) occurs
anywhere on the bus)
–
if Write Protect (W) is Low or if the addressed
page is in the region protected by the Block
Protect (BP1 and BP0) bits.
Figure 13. Byte Write (WRITE) Sequence
Note: Depending on the memory size, as shown in Table 6., the most significant address bits are Don’t Care.
AI01442D
C
D
S
Q
A7
2
1
3456789 10 11 12 13 14 15 16 17 18 19
A6 A5 A4 A3 A2 A1 A0
A8
20 21 22 23
High Impedance
Instruction
Byte Address
0
765432
0
1
Data Byte
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V32M4FJ-6 | 32M X 4 DDR DRAM, 0.7 ns, PBGA60 |
| MT46H16M32LFB5-6IT:C | 16M X 32 DDR DRAM, PBGA90 |
| ML1I-65656L-100CB | 32K X 8 STANDARD SRAM, 100 ns, CDIP28 |
| M95160-MB6TP | 2K X 8 SPI BUS SERIAL EEPROM, DSO8 |
| M95160-WMB3T | 2K X 8 SPI BUS SERIAL EEPROM, DSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M95010-WDW5T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-WDW6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-WDW6/W | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-WDW6G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95010-WDW6G/W | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock |
发布紧急采购，3分钟左右您将得到回复。