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参数资料
| 型号： | M95320-BN6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 4K X 8 SPI BUS SERIAL EEPROM, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 2/42页 |
| 文件大小： | 771K |
| 代理商： | M95320-BN6 |
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M95640, M95320
10/42
Figure 6. Hold Condition Activation
Status Register
Figure 7. shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 4. Status Register Format
Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
■
Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction
completion
–
Write Status Register (WRSR) instruction
completion
–
Write (WRITE) instruction completion
■
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
■
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
b7
b0
SRWD
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
相关PDF资料 |
PDF描述 |
|---|---|
| M95P-15-30-135 | PCB CONNECTOR, PLUG |
| M95S-15-30-135 | PCB CONNECTOR, SOCKET |
| MA-121-060-235-0200 | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
| MA-121-060-235-02WN | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
| MA-121-060-235-0500 | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M95320-BN6G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
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