- 您现在的位置：买卖IC网 > PDF目录180438 > M95320-BN6 (STMICROELECTRONICS) 4K X 8 SPI BUS SERIAL EEPROM, PDIP8 PDF资料下载
参数资料
| 型号： | M95320-BN6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 4K X 8 SPI BUS SERIAL EEPROM, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 7/42页 |
| 文件大小： | 771K |
| 代理商： | M95320-BN6 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
15/42
M95640, M95320
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 10..
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 4.) be-
comes
protected
against
Write
(WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
Figure 10. Read Status Register (RDSR) Sequence
C
D
S
2
1
3456789 10 11 12 13 14 15
Instruction
0
AI02031E
Q
7
6543210
Status Register Out
High Impedance
MSB
7
6543210
Status Register Out
MSB
7
相关PDF资料 |
PDF描述 |
|---|---|
| M95P-15-30-135 | PCB CONNECTOR, PLUG |
| M95S-15-30-135 | PCB CONNECTOR, SOCKET |
| MA-121-060-235-0200 | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
| MA-121-060-235-02WN | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
| MA-121-060-235-0500 | 60 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, RECEPTACLE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M95320-BN6G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6P | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6TG | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
| M95320-BN6TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock |
发布紧急采购，3分钟左右您将得到回复。