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参数资料
| 型号： | MA31751 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | Memory Management & Block Protection Unit |
| 中文描述： | 内存管理 |
| 文件页数： | 7/17页 |
| 文件大小： | 160K |
| 代理商： | MA31751 |
MA31751
7/17
MISCELLANEOUS
RESETN
CSN
ERROR INDICATION
MPROEN
Pin Name
Function
Description
Memory Protect Error
The MPROEN output is always asserted low when ASIN is low. On an
external memory cycle, MPROEN low at the end of the cycle indicates
there has been a protection error in either the MMU or the BPU. A high
indicates no error. MPROEN goes high after ASIN rising on XIO cycles.
This active-low output is asserted low if a parity error is detected during an
MMU/BPU memory transfer.
PRPEN
Page RAM Parity Error
System Reset
MMU Chip Select
Active low device reset input. Should be connected to system reset.
A low on this input selects the MMU. In a 1750A system, this input may be
tied to ground if MMU functions are required, or tied to MION if only BPU
functions are required (must be active for XIO cycles when the device may
need to respond to an MMU/BPU XIO command.) In 1750B, this input
should be derived by decoding the PB[0:3] bus from the CPU. (Note that in
1750B mode, one device is required per implemented page bank.)
This output becomes active (low) when MPROEN is valid if there is at least
one BPU present in the system .
This active-low input is used to select between the CPU and DMA protection
registers within the MA31751, and should be asserted low when the CPU
has relinquished control to a DMA in the system. DMAKN active low means
that the MMU gets the AS[0:3] and PS[0:3] information from the pins rather
than from the internal copy of the CPU Status Word. The signal is driven by
the system.
This active-high signal goes high in BPU mode following a system reset to
indicate that the memory system is globally write-protected. The signal is
set low by the XIO MPEN command. GPLE is inactive high when the BPU
functions are disabled.
A high on this output indicates that a memory cycle is a cache hit - a low
indicates a cache miss. This output goes low when ASIN is low and rises on
memory cycles when a hit has been validated. This output goes high on XIO
cycles.
BPUVALIDN
BPU enabled and
selected
DMA Acknowledge
DMAKN
GLPE
Global Protect Enable
HITMISSN
Cache hit/miss
VDD
GND
Power Supply
Ground
5V DC power supply input.
0V reference point.
POWER
Figure 6: Pin Description Table (continued)
相关PDF资料 |
PDF描述 |
|---|---|
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
| MA3693 | 1553B Bus Controller/Remote Terminal |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MA31753 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全称:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU与芯片冷却器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 电压额定值: 功率额定值: 速度: 气流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:Silicon planar type |
| MA3180-H | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:Silicon planar type |
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