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参数资料
| 型号： | MA3690 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | 1553B Bus Controller/Remote Terminal |
| 中文描述： | 1553B总线控制器/远程终端 |
| 文件页数： | 12/41页 |
| 文件大小： | 426K |
| 代理商： | MA3690 |
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MA3690/1/3
12/41
Word Count Low
This bit shall be reset to logic zero by the reception of any
valid command word with the exception of TSW, TLC and
TBW.
This bit shall be set to logic one if fewer valid data words
are received than specified by the preceding command word.
Word Count High
This bit shall be rest to logic zero by the reception of any
valid command word with the exception of TSW, TLC and
TBW.
This bit shall be set to logic one if the received message is
longer than stipulated by the preceeding command word.
Illegal Broadcast
This bit shall be reset to logic zero by the reception of any
valid command word with the exception of TSW, TLC and
TBW.
This bit shall be set to logic one if a valid command word
which by definition requires terminal transmission is received
with the broadcast address.
Bus 0 Shutdown
This bit shall be set to logic one if bus 0 is shutdown.
Bus 1 Shutdown
This bit shall be set to logic one if bus 1 is shutdown.
Terminal Flag Inhibited
This bit shall be set to logic one if the internal terminal flag
inhibit is set.
Transmitter Timeout on Bus 0
This bit shall be set to logic one if a transmitter timeout has
occured on bus 0.
Transmitter Timeout on Bus 1
This bit shall be set to logic one if a transmitter timeout has
occured on bus 1.
Note: RTAD0, RTAD1, RTAD2, RTAD3, RTAD4 define the RT
address RTADPAR odd parity with the address bits
BCSTEN0
- Broadcast enable for BUS0
BCSTEN1
- Broadcast enable for BUS1
Figure 4: Subsystem RT Address Buffer
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTADPAR
BUFFER
B0
B1
B2
B3
B4
B5
B6
B7
BCSTEN0
BCSTEN1
ADEN
EN
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