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参数资料
| 型号： | MA3693 |
| 厂商： | Dynex Semiconductor Ltd. |
| 英文描述： | 1553B Bus Controller/Remote Terminal |
| 中文描述： | 1553B总线控制器/远程终端 |
| 文件页数： | 3/41页 |
| 文件大小： | 426K |
| 代理商： | MA3693 |
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MA3690/1/3
3/41
INCADRN
INCREMENT ADDRESS - This line pulses low to increment
the external instruction addressing counter.
Output
HSFN/IRQN
Output
HANDSHAKE FAIL / INTERRUPT REQUEST
RT: This line pulses low to inform the subsystem that it has
not responded to a data transfer request to take place.
BC: This line pulses low to generate an interrupt to the BC
subsystem processor.
INCMDN
IN COMMAND - When low this line indicates that the terminal
is currently servicing a command word.
Output
EOTN
END OF TRANSMISSION - When low this line indicates that
the selected bus is quiet and hence available for use.
Output
ABORTN
This line will pulse low to abort execution of the current
command if an error is detected.
Output
B0-B15
HIGHWAY LINES - 16 line bidirectional Output data highway.
(B0 = LSB).
Input/Output
CLDN
COMMAND LOAD - When low this line indicates that the
word on the data highway should be loaded into the
transmitter for transmission with a command sync.
Inter-chip (CMOS)
DLDN
DATA LOAD - When low this line indicates that the word on
the data highway should be loaded into the transmitter for
transmission with a data sync.
Inter-chip (CMOS)
OBFN
OUTPUT BUFFER FULL - When low this line indicates that
the transmitter output buffer is full and cannot be overwritten.
Inter-chip (CMOS)
VALDRN
VALID DATA RECEIVED - When low this line indicates that a
valid data word has been received and is on the data
highway.
Inter-chip (CMOS)
VALCRN
VALID COMMAND RECEIVED -
RT: When low this line indicates that a valid command word
for this RT has been received.
BC: When low this line indicates that a valid word with a
command sync has been received.
Inter-chip (CMOS)
RT/BCN
REMOTE TERMINAL/BUS CONTROLLER - When high the
terminal will function as an RT.When low the terminal will
function as a bus controller.
Input
CK4
4MHz system clock.
Output
PUCN
POWER UP CLEAR - This line should be pulsed low
following power-up.
Input
RESETN
RESET - This line when low, forces the internal circuitry to
reset to the quiescent initialised state. This is a ‘TTL’ level
input on both devices and an open-drain output on the
MA3690. The subsystem should drive this line via an open
drain/collector device with external pull up fitted.
Input/Output
RT0 / RT1
REPLY TIMEOUT DECODE - These lines on the MA3690
allow four different timeout values to be used. On the
MA3693, the RT1 signal is not available and is pulled down
internally.
Inputs
RT1
RT0
Timeout (us)
0
0
1
1
0
1
0
1
16
22
44
108
Note: Under normal operation, option 00 should be used.
(i.e. 16uS)
The measurement is taken between mid parity and mid sync
- measured at PDIN/NDIN terminals.
TF
TERMINAL FLAG - This line is available only on the 64-pin
MA3690 and on the MA3693 (where it replaces RT1). The
line indicates the state of the Terminal Flag bit in the Status
Word, and can be inhibited by the mode code Inhibit
Terminal Flag. This is an active LOW signal.
Output
TEST/SOT
These lines are for test purposes only and for normal chip set
operation must both be tied low.
Inputs
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