参数资料
型号: MA7001
厂商: Dynex Semiconductor Ltd.
英文描述: Radiation Hard 512x9 Bit FIFO
中文描述: 辐射硬512x9位的FIFO
文件页数: 6/15页
文件大小: 144K
代理商: MA7001
MA7001
6/15
SIGNAL DESCRIPTIONS
Reset (RS)
Reset occurs when
RS
is in a low state, setting both read and
write pointers to the first location in memory. Reset is required
prior to the first write. Both READ (
R
) and WRITE (
W
) signals
must be in high states during reset.
Read Enable (
R
):
Providing the EMPTY FLAG (
EF
) is not set, i.e. there is still
data to be read, a read cycle commences on the falling edge of
R, (see Figure 16). Data is read in a First-ln First-Out manner
independent of write operations. When reads are disabled
data outputs (Q0 - Q8) are in a high impedance state. Reading
the last available memory location sets the EMPTY FLAG
(
EF
), which is cleared following a write cycle.
Write Enable (
W
):
Providing the FULL FLAG (
FF
) is not set, i.e. there exists at
least one memory location for writing, a write cycle
commences on the falling edge of (
W
), (see Figure 17). Data is
written into consecutive memory locations independent of read
operations on the rising edge of W. Data set up and hold times
are with respect to the rising edge of
W
.
Expansion In (
Xl
):
There are two possible modes of operation for the FIFO. One
with
Xl
grounded in which the device is in singledevice mode,
the other is a depth expension mode or daisy chain
configuration. In the latter mode
Xl
inputs come from
EXPANSION OUT (
XO
) outputs of the device preceding it in
the chain.
Expansion Out (
XO
):
In depth expansion mode
XO
from one device signals the next
device in the chain that the last location in its memory has been
accessed.
Full Flag (
FF
):
FF
becomes active when the last available memory location
has been written to, (see Figure 18). In general, this occurs
whenever the write pointer coincides with the read pointer
following a write cycle. Writes are inhibited while
FF
is active,
and may only proceed after a read cycle has occured.
FF
will go high t
RFF
after completion of a valid READ operation.
FF
will go low t
WFF
from the beginning of a subsequent WRITE
operation, provided that a second READ has not been
completed. Writes beginning t
FFW
after
FF
goes high, are valid.
Writes beginning after
FF
goes low and ending more than t
WPI
before FF goes high, are invalid (ignored). Writes beginning
less than twpl before
FF
goes high and less than t
FFW
later,
may or may not occur (be valid) depending on the internal flag
status (see Figure 19).
If a Write to the last but one physical location completes while
the last location (511th) is being Read, the
FF
will not be
activated. The next Read should start after the last Write has
completed.
As a WRITE operation is being performed to the last physical
memory location (511th) whilst the READ pointer is waiting at
the 510th physical location the FULL flag is activated for a
duration less than 20ns.
Note: The last physical location (511th) is accessed after 511
WRITE or READ operations after RESET.
Empty Flag (
EF
):
Following an initial RESET
EF
is active, becoming inactive
after the first write cycle, (see Figure 20).
EF
becomes active
once the read and write pointers are coincident following a
read cycle. Reading will not take place whilst
EF
is active, and
may only proceed once a write cycle has occured.
EF
will go high t
WEF
after completion of a valid WRITE
operation.
EF
will again go low t
REF
from the beginning of a
subsequent READ operation, provided that a second WRITE
has not been completed. Reads beginning t
EFR
after
EF
goes
high, are valid. Reads begun after
EF
goes low and ending
more than t
RPI
before
EF
goes high, are invalid (ignored).
Reads beginning less than t
RIP
before
EF
goes high and less
than t
EFR
later, may or may not occur (be valid) depending on
the internal flag status (See Figure 21). If a Read to the last but
one physical location completes while the last location (511th)
is being written, the
EF
will not be activated. The next Read
should be activated after the last Write has completed.
First Load/Retransmit (
FL
/
RT
):
This is a dual purpose input depending on the mode of
operation of the device. In single device mode
Xl
= 0 data may
be retransmitted, i.e. it may be re-read. In depth expansion
mode
FL
signifies the first device in the chain. When
RT
is
pulsed low the read pointer is set to the first memory location.
The write pointer is unaffected. This feature is disabled in
depth expansion mode, and can only be applied when
R
and
W
are inactive (See Figure 22).
Data Inputs (D0 - D8):
Data inputs, 9 bit word, for write
operations.
Data Outputs (Q0 - Q8):
Data outputs, 9 bit word, for read operations. When
R
is
inactive these outputs are in a high impedance state.
相关PDF资料
PDF描述
MA9264 Radiation Hard 8192x8 Bit Static RAM
MAC15S Sensitive Gate Triacs Silicon Bidirectional Thyristors
MAC15SDG Sensitive Gate Triacs Silicon Bidirectional Thyristors
MAC15SMG Sensitive Gate Triacs Silicon Bidirectional Thyristors
MAC15SNG Sensitive Gate Triacs Silicon Bidirectional Thyristors
相关代理商/技术参数
参数描述
MA700A 制造商:Panasonic Industrial Company 功能描述:DIODE
MA700A-(TA5) 制造商:Panasonic Industrial Company 功能描述:DIODE
MA700AABC001 制造商:未知厂家 制造商全称:未知厂家 功能描述:Pantheon Antenna 3in1 MA.700 Screw-Mount
MA700AABC002 制造商:未知厂家 制造商全称:未知厂家 功能描述:Pantheon Antenna 3in1 MA.700 Screw-Mount
MA700ATA 制造商:Panasonic Industrial Company 功能描述:DIODESUB:MA2C700A0F