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参数资料
| 型号： | MA838 |
| 厂商： | Zarlink Semiconductor Inc. |
| 英文描述： | SINGLE PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR |
| 中文描述： | 单相脉宽调制波形发生器 |
| 文件页数： | 10/13页 |
| 文件大小： | 314K |
| 代理商： | MA838 |
9
MA838
POWER-UP C0NDITIONS
All bits in both the Initialisation and Control registers power-
up in the low state. This means that Counter Reset (
CR
) is
active and a 50% duty cycle will be output from all PWM outputs
until further initialising action is taken. Holding
RST
low or
using the SET TRIP input will ensure that the PWM outputs
remain inactive (i.e., low) during this period.
MA838 PROGRAMMING EXAMPLE
The following example assumes that a master clock of
12·288 MHz is used (12·288 MHz crystals are readily available).
This clock frequency will allow a maximum carrier frequency of
24 kHz and a maximum power frequency of 4 kHz.
Initialisation Register Programming Example
A power waveform range of up to 250Hz is required with a
carrier frequency of 6kHz, a pulse deletion time of 10μs and an
underlap of 5μs.
1. Setting the carrier frequency
The carrier frequency should be set first as the power
frequency, pulse deletion time and pulse delay time are all
defined relative to the carrier frequency.
We must calculate the value of
n
that will give the required
carrier frequency:
k
512 x
n
From Table 4,
n
= 4 corresponds to a 3-bit CFS word of
010 in temporary register R1.
2. Setting the power frequency range
We must calculate the value of
m
that will give the required
power frequency:
f
RANGE
=
384
From Table 5,
m
= 16 corresponds to a 3-bit FRS word of
100 in temporary register R1.
3. Setting the pulse delay time
As the pulse delay time affects the actual minimum pulse
width seen at the PWM outputs, it is sensible to set the pulse
delay time before the pulse deletion time, so that the effect of
the pulse delay time can be allowed for when setting the pulse
deletion time.
We must calculate the value of
pdy
that will give the required
pulse delay time:
However, the value of
pdy
must be an integer. As the
purpose of the pulse delay is to prevent ‘shoot-through’ (where
both top and bottom arms of the inverter are on simultaneously),
it is sensible to round the pulse delay time up to a higher, rather
than a lower figure.
Thus, if we assign the value 16 to
pdy
this gives a delay time
of 5·2μs. From Table 6,
pdy
= 16 corresponds to a 6-bit PDY
word of 110000 in temporary register R2.
f
CARR
=
n
=
=
=
4
x
m
m
=
=
f
CARR
=
16
pdy
=
t
pdy
x
f
CARR
x 512
= 5 x 10
-6
x 6 x 10
3
x 512 =
15·4
t
pdy
=
pdy
f
CARR
x 512
f
CARR
f
RANGE
x 384
250 x 384
6 x 10
3
k
512 x
f
CARR
12·288x10
6
512 x 6 x 10
3
pdt
=
f
pd
x
f
CARR
x 512
= 15·2 x 10
-6
x 6 x 10
3
x 512 =
46·7
t
pd
=
pdt
f
CARR
x 512
4. Setting the pulse deletion time
In setting the pulse deletion time (i.e., the minimum pulse
width) account must be taken of the pulse delay time, as the
actual minimum pulse width seen at the PWM outputs is equal
to
t
pd
–
t
pdy
.
Therefore, the value of the pulse deletion time must, in this
instance, be set 5·2μs longer than the minimum pulse length
required
Minimum pulse length required = 10μs
∴
t
PD
to be set to 10μs + 5·2μs = +15·2μs
Now,
Again,
pdt
must be an integer and so must be either rounded
up or down – the choice of which will depend on the application.
Assuming we choose in this case the value 46 for
pdt
, this gives
a value of
t
, of 15 μs and an actual minimum pulse width of
15 – 5·2μs = 9·8μs.
From Table 7,
pdt
= 46 corresponds to a value of PDT, the
7-bit word in temporary register R0 of 1010010.
The data which must be programmed into the three temporary
registers R0, R1 and R2 (for transter into the initialisation
register) in order to achieve the parameters in the example
given, is shown in Fig. 15.
Control Register Programming Example
The control register would normally be updated many times
while the motor is running, but just one example is given here.
It is assumed that the initialisation register has already heen
programmed with the parameters given in the previous example.
A power waveform of 100Hz is required with a PWM
waveform amplitude of 80% of that stored in the ROM. The
outputs should be enabled and no overmodulation is required.
Fig. 15
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