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参数资料
| 型号： | MACH120-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 13/20页 |
| 文件大小： | 171K |
| 代理商： | MACH120-15JC |
MACH120-12/15
21
MACH
1
&
2
Families
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up.
Following power-up, all ip-ops will be reset to LOW. The output state will depend on the logic
polarity. This feature provides extra exibility to the designer and is especially valuable in sim-
plifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise
to its steady state, two conditions are required to insure a valid power-up reset. These conditions
are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback
setup times are met.
Power-Up Reset Waveform
Parameter
Symbol
Parameter Descriptions
Max
Unit
tPR
Power-Up Reset Time
10
s
tS
Input or Feedback Setup Time
See
Switching
Characteristics
tWL
Clock Width LOW
14129J-16
tPR
tWL
tS
4 V
VCC
Power
Registered
Output
Clock
相关PDF资料 |
PDF描述 |
|---|---|
| MACH120-12 | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-15YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-5YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-7YC | High-Performance EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH120-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
| MACH120-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH130-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
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