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参数资料
| 型号： | MACH120-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High-Performance EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 18/20页 |
| 文件大小： | 171K |
| 代理商： | MACH120-15JC |
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MACH120-12/15
The Macrocell
The MACH120 macrocells can be congured as either registered or combinatorial, with programmable
polarity. The macrocell provides internal feedback whether congured as registered or combinatorial.
The ip-ops can be congured as D-type or T-type, allowing for product-term optimization.
The ip-ops can individually select one of four global clock pins, which are also available as
logic inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The
ip-ops can also be asynchronously initialized with the common asynchronous reset and preset
product terms.
The I/O Cell
The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can
be congured in one of three ways: always enabled, always disabled, or controlled by a product
term. If product term control is chosen, one of two product terms may be used to provide the
control. The two product terms that are available are common to six I/O cells. Within each PAL
block, two product terms are available for selection by the rst six three-state outputs; two other
product terms are available for selection by the last six three-state outputs.
These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or
a three-state output for use in driving a bus.
SpeedLocking for Guaranteed Fixed Timing
The unique MACH 1 architecture is designed for high performance—a metric that is met in both
raw speed, but even more importantly, guaranteed xed speed. Using the design of the central
switch matrix, the MACH 120 product offers the SpeedLocking feature, which allows a stable
xed pin-to-pin delay, independent of logic paths, routing resources and design rets for up to
16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product
terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine
for continuous, high performance required in today's demanding designs
相关PDF资料 |
PDF描述 |
|---|---|
| MACH120-12 | High-Performance EE CMOS Programmable Logic |
| MACH131SP-12YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-15YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-5YC | High-Performance EE CMOS Programmable Logic |
| MACH131SP-7YC | High-Performance EE CMOS Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MACH120-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
| MACH120-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:High-Density EE CMOS Programmable Logic |
| MACH130-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACH130-15JC-18JI | 制造商:Advanced Micro Devices 功能描述: |
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