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参数资料
| 型号： | MAS3507D |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | 通用总线功能 |
| 英文描述： | MPEG 1/2 Layer 2/3 Audio Decoder |
| 中文描述： | 的MPEG 1 / 2 2 / 3层音频解码器 |
| 文件页数： | 19/60页 |
| 文件大小： | 867K |
| 代理商： | MAS3507D |
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PRELIMINARY DATA SHEET
MAS 3507D
Micronas
19
Note: S =
I
2
C-Bus Start Condition from master
I
2
C-Bus Stop Condition from master
ACK = Acknowledge-Bit: LOW on I2C_DA from slave or master
NAK =
Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate ‘End of Read’
P =
Wait = I
2
C-Clock line is held low, while the MAS 3507D is processing the I
2
C command.
Fig. 3–1:
I
2
C bus protocol (MSB first; data must be stable while clock is high)
3.2. Command Structure
The I
2
C control of the MAS 3507D is done completely
via the I
2
C data register by using a special command
syntax. The commands are executed by the
MAS 3507D during its normal operation without any
loss or interruption of the incoming data or outgoing
audio data stream. These I
2
C commands allow the
controller to access internal states, RAM contents,
internal hardware control registers, and even a down-
load of an alternative software module. The command
structure
allows
sophisticated
MAS 3507D. The registers of the MAS 3507D are
either general purpose, e.g. for program flow control,
or specialized registers that directly affect hardware
blocks. The unrestricted access to these registers
allows the system controller to overrule the firmware
configuration of the serial interfaces or the default input
line selection.
control
of
the
The control interface is also used for low bit rate data
transmission, e.g. MPEG-embedded ancillary data
transmission. The data information is performed by
sending a ‘read memory’
command to the MAS 3507D
and by reading the memory block that temporarily con-
tains the required information. The synchronization
between the controller and the MAS 3507D is done via
a MPEG-FRAME-SYNC signal or by monitoring the
MPEGFrameCount register (at the cost of a higher
work load for the controller).
The MAS 3507D firmware scans the I
2
C interface peri-
odically and checks for pending or new commands.
However, due to some time critical firmware parts, a
certain latency time for the response has to be
expected. The theoretical worst case response time
does not exceed 4 ms.
Table 3–4 shows the basic con-
troller
commands
that
MAS 3507D.
are
available
by
the
3.2.1. The Internal Fixed Point Number Format
Internal register or memory values can easily be
accessed via the I
2
C interface. In this document, two
number representations are used: the fixed point nota-
tion ‘v’ and the 2’s complement number notation ‘r’.
The conversion between the two forms of notation is
easily done (see the following equations).
r = v x 524288.0 + 0.5; (
1.0
≤
v < 1.0)
v = r / 524288.0; (
524288 < r < 524287)
(EQ 1)
(EQ 2)
1
0
S
P
I2C_DA
I2C_CL
相关PDF资料 |
PDF描述 |
|---|---|
| MAS3559F | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS35x9F | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3509F | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3519F | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3529F | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAS3509F | 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3519F | 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3529F | 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3539F | 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| MAS3549F | 制造商:MICRONAS 制造商全称:MICRONAS 功能描述:MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
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