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参数资料
| 型号： | MAS3549F |
| 厂商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分类： | Codec |
| 英文描述： | MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec |
| 中文描述： | 新加坡金融管理局35x9F的MPEG 2 / 3层，AAC音频解码器，G.729的附件A编解码器 |
| 文件页数： | 11/92页 |
| 文件大小： | 1186K |
| 代理商： | MAS3549F |
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DATA SHEET
MAS 35x9F
Micronas
June 30, 2004; 6251-505-1DS
11
2.4.3. D/A Converters
One pair of Micronas’ unique multibit sigma-delta D/A
converters is used to convert the audio data with high
linearity and a superior S/N. In order to attenuate high-
frequency noise caused by noise-shaping, internal
low-pass filters are included. They require additional
external capacitors between pins FILTx and OUTx
(see Section 5.1. on page 89).
2.4.4. Output Amplifiers
The integrated output amplifiers are capable of directly
driving stereo headphones or loudspeakers of 16 to
32
impedance via 22
series resistors. If more out-
put power is required, the right output signal can be
inverted and a single loudspeaker can be connected
as a bridge between pins OUTL and OUTR. In this
case, the source should be set to mono for optimized
power.
Fig. 2–6:
Bridge operation mode
2.5. Clock Management
The MAS 35x9F is driven by a single crystal-controlled
clock with a frequency of 18.432 MHz. It is possible to
drive the MAS 35x9F with other reference clocks. In
this case, the nominal crystal frequency must be writ-
ten into memory location D0:348. The crystal clock
acts as a reference for the embedded synthesizer that
generates the internal clock.
For compressed audio data reception, the MAS 35x9F
may act either as the clock master (Demand Mode) or
as a slave (Broadcast Mode) as defined by bit[1] in
IOControlMain memory cell (see Table 3–8 on
page 32). In both modes, the output of the clock syn-
thesizer depends on the sample rate of the decoded
data stream as shown in Table 2–1.
In the BROADCAST MODE (PLL on), the incoming
audio data controls the clock synthesizer via a PLL.
In the DEMAND MODE (PLL off) the MAS 35x9F acts
as the system master clock. The data transfer is trig-
gered by a demand signal at pin EOD.
2.5.1. DSP Clock
The DSP clock has a separate divider. In order to
reduce the power consumption, it is set to the lowest
acceptable rate of the synthesizer clock which is capa-
ble to allow the processor core to perform all tasks.
2.5.2. Clock Output At CLKO
If the DSP or audio codec functions are enabled
(bits[11] or [10] in the Control Register at I
2
C subad-
dress 6A
hex
), the reference clock at pin CLKO is
derived from the synthesizer clock.
Dependent on the sample rate of the decoded signal a
scaler is applied which automatically divides the clock-
out by 1, 2, or 4, as shown in Table 2–1. An additional
division by 2 may be selected by setting bit[17] of the
OutClkConfig memory cell (see Table 3–8 on
page 32). The scaler can be disabled by setting bit[8]
of this cell.
The controlling at OutClkConfig is only possible as
long as the DSP is operational (bit[10] of the Control
Register). Settings remain valid if the DSP is disabled
by clearing bit[10].
R
≥
32
MASF
DAC
DAC
OUTL
OUTR
Table 2–1:
Settings of bits[8] and [17] in OutClkConfig
and resulting CLKO output frequencies
f
s
/kHz
Output Frequency at CLKO/MHz
Synth.
Clock
bit[8]=1
Scaler On
bit[8]=0, bit[17]=0
Scaler Plus
Extra Division
bit[8]=0, bit[17]=1
48
24.576
512
f
s
24.576
256
f
s
12.288
44.1
22.5792
22.5792
11.2896
32
24.576
768
f
s
24.576
384
f
s
12.288
24
512
f
s
12.288
256
f
s
6.144
22.05
22.5792
11.2896
5.6448
16
24.576
768
f
s
12.288
384
f
s
6.144
12
512
f
s
6.144
256
f
s
3.072
11.025
22.5792
5.6448
2.8224
8
24.576
768
f
s
6.144
384
f
s
3.072
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| MAS3587F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MPEG Layer 3 Audio Encoder/Decoder |
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