参数资料
型号: MAS3549F
厂商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分类: Codec
英文描述: MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec
中文描述: 新加坡金融管理局35x9F的MPEG 2 / 3层,AAC音频解码器,G.729的附件A编解码器
文件页数: 34/92页
文件大小: 1186K
代理商: MAS3549F
MAS 35x9F
DATA SHEET
34
June 30, 2004; 6251-505-1DS
Micronas
D0:347
Interface Status Control
(reset = 05
hex
)
This control cell allows to enable/disable the data I/O interfaces. In addition,
the clock of the output data interface interfaces, S/PDIF and SDO, can be set
to a low-impedance mode.
MPEG
bit[6]
S/PDIF input selection (used for download modules)
0 (reset)
select S/PDIF input 1
1
select S/PDIF input 2
bit[5]
Enable/disable S/PDIF output
0 (reset)
enable S/PDIF output
1
S/PDIF output (invalid)
bit[4]
Reserved, must be set to zero
bit[3]
Enable/disable serial data output SDO
0 (reset)
SDO valid data
1
SDO invalid data
bit[2]
Output clock characteristic (SDO and S/PDIF outputs)
0
low impedance
1 (reset)
high impedance
bit[1]
reserved, must be set to zero
Enable/Disable SDI
1)
0
enable
1 (reset)
disable
Both digital outputs, S/PDIF and I
2
S, and the D/A converters may use the
decoded audio independent of each other.
bit[0]
Changes at this memory address must be validated by setting bit[0] of
D0:346
hex
.
InterfaceControl
D0:348
Oscillator Frequency
(reset = 18432
dec
)
bit[19:0]
oscillator frequency in kHz
All
In order to achieve a correct internal operating frequency of the DSP, the nom-
inal crystal frequency has to be deposited into this memory cell.
Changes at this memory address must be validated by setting bit[0] of
D0:346
hex
.
OfreqControl
1)
Note:
The pins SIC, SII, SID are switched to output mode, if bit [0] = 1 (Reset value).
Table 3–9:
D0 control memory cells, continued
Memory
Address
(hex)
Function
Name
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