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参数资料
| 型号： | MAX1005CEE+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 7/8页 |
| 文件大小： | 0K |
| 描述： | IC UNDERSAMPLER IF 16-QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 100 |
| 功能： | IF 欠采样器 |
| RF 型： | PCS，PHS，WLL |
| 次要属性： | 并行逻辑接口 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
IF Undersampler
SAMPLE
SAMPLE
01111
01110
ANALOG
INPUT
n
SAMPLE
n+1
n+2
00010
00001
CLK
00000
D0–D4
n-1
n
n+1
11111
11110
11101
10001
10000
t DO
Figure 3. Receive ADC Timing Diagram
Operating Modes
The MAX1005 has three operating modes: transmit,
receive, and shutdown. The operating mode is selected
- FS
COM
INPUT VOLTAGE (LSB)
+FS
by the RXEN and TXEN inputs, as shown in Table 2.
In transmit mode, the DAC is active and the ADC is
inactive. Power consumption is typically 16.5mW with a
Figure 1. Receive ADC Transfer Function
CLK
3V supply voltage. In receive mode, the ADC is active
and the DAC is inactive. Power consumption in this
mode is typically 39mW with a 3V supply voltage.
The third mode is shutdown, in which both the DAC
and the ADC are inactive. Select this mode by setting
DAC
INPUT
DATA
n-1
t DS
n
n+1
n+2
RXEN = TXEN at any voltage from DGND to VCCD. In
shutdown mode, the CLK input can continue to run
without damaging the device and with no significant
(D0–D6)
increase in the typical shutdown supply current specifi-
DAC
OUTPUT
n-1
t HOLD
n
n+1
cation of 0.1μA. When exiting shutdown, the MAX1005
is guaranteed to be operational within 2.4μs after TXEN
or RXEN is asserted, as shown in Table 2.
Figure 2. Transmit DAC Timing Diagram
Digital Interface
The DAC has a 7-bit parallel digital interface. Figure 2
shows the timing diagram for the transmit DAC. Digital
data is latched into the DAC input register on the falling
To prevent supply-current drain due to leakage cur-
rents from entering the ADC output bits, the ADC out-
puts (D0–D4) should not be held high in low-power
shutdown mode.
Table 2. Operating Mode Selection
edge of CLK. On the next rising edge of CLK the data
is transferred to the DAC register and the DAC output
voltage is updated.
The ADC is enabled by setting TXEN = 0 and RXEN =
1. Figure 3 shows the ADC timing diagram. Input data
is sampled on the falling edge of CLK, while output
data changes state on the rising edge of CLK. This
minimizes digital feedthrough and noise while the ana-
log input is being sampled. The ADC output data is
RXEN
0
0
1
1
TXEN
0
1
0
1
OPERATING MODE
Low-power shutdown: ADC and DAC
disabled
Transmit mode: DAC active, ADC disabled
Receive mode: ADC active, DAC disabled
Low-power shutdown: ADC and DAC
disabled
applied to the 5-bit parallel output pins (D0–D4), with
the MSB at D4.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1005CEE+ | 功能描述:射频无线杂项 IF Undersampler RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005CEE+T | 功能描述:射频无线杂项 IF Undersampler RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005CEE-T | 功能描述:射频无线杂项 RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005EEE | 功能描述:射频无线杂项 RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| MAX1005EEE+ | 功能描述:射频无线杂项 IF Undersampler RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
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