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| 型号： | MAX11008EVKIT+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 54/67页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MAX11008 BIAS CTLR |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 偏压控制器 |
| 适用于相关产品： | MAX11008 |
| 已供物品： | 板，模块 |
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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 13a. Channel 2 Averaging Equation
(T2AVGCTL)
D15
0
1
CHANNEL 2 AVERAGING EQUATION
Average = average + 1/16 difference.
Average = average + 1/4 difference.
Table 13b. Channel 2 Difference Limiter Bits (T2LIMIT[2:0])
D14
0
0
0
0
1
1
1
1
D13
0
0
1
1
0
0
1
1
D12
0
1
0
1
0
1
0
1
CHANNEL 2 DIFFERENCE LIMITER
No limiting is applied.
Difference is limited to 1 LSB (1/8 of a degree).
Difference is limited to 3 LSBs (3/8 of a degree).
Difference is limited to 7 LSBs (7/8 of a degree).
Difference is limited to 15 LSBs (1 7/8 degrees).
Difference is limited to 31 LSBs (3 7/8 degrees).
Difference is limited to 63 LSBs (7 7/8 degrees).
Difference is limited to 127 LSBs (15 7/8 degrees).
Table 13c. APC Parameter Source Select Bits (APCSRC_1, APCSRC_0)
APCSRC_1
0
0
1
1
APCSRC_0
0
1
0
1
APC PARAMETER SOURCE SELECT
Value stored in APC parameter register.
Reserved. Do not use.
Drain current samples.
External input samples (AIN input).
The A_HIST register bits A_HIST[3:0] set the APC hys-
teresis limits for both channel 1 and channel 2 V GATE_
calculations. After a new APC sample, the device pro-
ceeds in performing a V GATE_ calculation if that sample
differs from the previous sample used for a V GATE_ cal-
culation by an amount greater than the hysteresis set-
ting (see Table 16e). Set APCCOMP_ and TCOMP_ to 0
before A_HIST is changed.
DAC Input Registers (IDAC1, IDAC2) (Write Only)
DAC_[11:0] set the value of the DAC Input registers
(see Table 17). Bits D[15:12] are don’t-care bits. The
GATE_ output is not updated with this value until it is
transferred to the DAC Output register. Write to the
Load DAC register to transfer the contents of the DAC
Input register to the DAC Output register. Write directly
to the DAC Input register to manipulate the DAC output
without triggering a V GATE_ calculation.
DAC Input and Output Registers (IODAC1, IODAC2)
(Write Only)
DAC_[11:0] set the values of the input and output regis-
ters of the respective DACs (see Table 18). Writing to
this register does not trigger a V GATE_ calculation, but
the GATE_ output is immediately updated with the
value that is written to this register. Bits D[15:12] are
don ’t-care bits. The contents of the DAC Input and
Output registers are not stored in the EEPROM.
PGA Calibration Control Register (PGACAL)
(Write Only)
The PGA Calibration Control register selects the PGA
calibration mode and controls when calibrations occur
(see Table 19). Bits D[15:3] are don’t-care bits. The
data contained in the PGA Calibration Control register
is stored in the EEPROM.
Set TRACK to 0 to perform the next PGA calibration in
acquisition mode, and set TRACK to 1 to perform the
next PGA calibration in tracking mode. Leave TRACK
set to 0 the first time a PGA calibration is performed
after power-up.
Set DOCAL to 1 to perform calibrations of PGA1 and
PGA2. DOCAL resets to 0 after the PGA calibration rou-
tine is complete. If either channel is powered down, the
PGA calibration for that channel is bypassed.
54
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