参数资料
型号: MAX11100EUB+T
厂商: Maxim Integrated Products
文件页数: 3/19页
文件大小: 0K
描述: IC ADC 16BIT SRL 200KSPS 10UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
位数: 16
采样率(每秒): 200k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 444mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-uMAX
包装: 标准包装
输入数目和类型: 1 个单端,单极
其它名称: MAX11100EUB+TDKR
Maxim Integrated Products 11
MAX11100
16-Bit, +5V, 200ksps ADC with 10A Shutdown
Variations in frequency, duty cycle, or other aspects of
the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence. The
analog input is stored in the capacitive DAC, DOUT
changes from high impedance to logic-low, and the ADC
begins to convert after the sixth clock cycle. SCLK drives
the conversion process and shifts out the conversion
result on DOUT.
SCLK begins shifting out the data (MSB first) after the fall-
ing edge of the 8th SCLK pulse. Twenty-four falling clock
edges are needed to shift out the eight leading zeros
and 16 data bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to the
rising edge of CS, produce trailing zeros at DOUT and
have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX11100 in
shutdown. For maximum throughput, force CS low again
to initiate the next conversion immediately after the speci-
fied minimum time (tCSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX11100 in shutdown.
Figure 6. External Timing Diagram
Figure 7. Shutdown Sequence
CS
SCLK
20
16
24
12
14
8
6
DOUT
D15 D14 D13 D12 D11 D10
D9
D1
D0
D8
D5
D4
D3
D2
D7
D6
tCSH
tTR
tDO
tACQ
tCSS
tCH
tCL
tDV
COMPLETE CONVERSION SEQUENCE
CONVERSION 0
CONVERSION 1
POWERED UP
POWERED DOWN
DOUT
CS
TIMING NOT TO SCALE.
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