参数资料
型号: MAX11100EUB+T
厂商: Maxim Integrated Products
文件页数: 5/19页
文件大小: 0K
描述: IC ADC 16BIT SRL 200KSPS 10UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
位数: 16
采样率(每秒): 200k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 444mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-uMAX
包装: 标准包装
输入数目和类型: 1 个单端,单极
其它名称: MAX11100EUB+TDKR
Maxim Integrated Products 13
MAX11100
16-Bit, +5V, 200ksps ADC with 10A Shutdown
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
Serial Interfaces
The MAX11100’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s
serial interface as master, so that the CPU generates the
serial clock for the MAX11100. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull CS low.
2) Activate SCLK for a minimum of 24 clock cycles. The
serial data stream of eight leading zeros followed by
the MSB of the conversion result begins at the fall-
ing edge of CS. DOUT transitions on SCLK’s falling
edge and the output is available in MSB-first format.
Observe the SCLK to DOUT valid timing characteris-
tic. Clock data into the FP on SCLK’s rising edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
4) With CS high, wait at least 50ns (tCSW) before start-
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
A0
A1
CLK
CHANGE MUX INPUT HERE
CONVERSION
IN1
A0
A1
IN2
IN3
IN4
OUT
ACQUISITION
4-TO-1
MUX
AIN
CS
MAX11100
CS
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