参数资料
型号: MAX11359AETL+T
厂商: Maxim Integrated Products
文件页数: 54/67页
文件大小: 0K
描述: IC DAS SYSTEM 16BIT 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 数据采集系统(DAS)
分辨率(位): 16 b
采样率(每秒): 512
数据接口: MICROWIRE?,QSPI?,串行,SPI?
电压电源: 模拟和数字
电源电压: 1.8 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
58
Maxim Integrated
With the SLEEP or
SLEEP function deasserted on
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
With the SLEEP or
SLEEP function deasserted,
assert WU or
WU (wake-up) function on UPIO.
With the SLEEP or
SLEEP function deasserted, the
day alarm triggers.
Wake-Up
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX11359A to exit sleep mode, if in sleep mode. A
wake-up event in normal mode results only in a wake-up
event being recorded in the STATUS register.
RESET
The
RESET output pulls low for any one of the following
cases: power-on reset, DVDD monitor trips and RSTE =
0, watchdog timer expires, crystal oscillator is attached,
and 32kHz clock not ready.
The
RESET output can be turned off through the RSTE
bit in the PS_VMONS register, causing DVDD low sup-
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
Cs that operate with VDVDD < 1.8V.
Driving UPIO Outputs to AVDD Levels
UPIO outputs can be driven to AVDD levels in systems
with separate AVDD and DVDD supplies. Disable the
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the system’s analog
supply to AVDD and CPOUT. Setting UPIO outputs to
drive to CPOUT results in AVDD-referenced logic levels.
Supply Voltage Measurement
The AVDD supply voltage can be measured with the
ADC by reversing the normal input and reference sig-
nal s. The REF voltage is applied to one multiplexer
input, and AGND is selected in the other. The AVDD
signal is then switched in as the ADC reference voltage
and a conversion is performed. The AVDD value can
then be calculated directly as:
VAVDD = (VREF x Gain x 65536)/N
where VREF is the reference voltage for the ADC, Gain
is the PGA gain before the ADC, and N is the ADC
result. Note the AVDD voltage must be greater than the
gained-up REF voltage (VAVDD > VREF x Gain). This
measurement must be done in unipolar mode.
0000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0010
65,535
65,533
INPUT VOLTAGE (LSB)
B
INA
RY
O
UT
P
UT
CO
DE
1111 1111 1111 1101
1111 1111 1111 1110
1111 1111 1111 1111
1 LSB =
VREF
(GAIN x 65,536)
0
2
VREF/GAIN
V
REF
/GAIN
13
1111 1111 1111 1100
0000 0000 0000 0011
FULL-SCALE TRANSITION
Figure 20. ADC Unipolar Transfer Function
MAX11359A
DAC A
OUTA
FBA
Figure 22. DAC Unipolar Output Circuit
0+1
-1
1000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0010
+32,767
+32,765
INPUT VOLTAGE (LSB)
B
INA
RY
O
UT
P
UT
CO
DE
0111 1111 1111 1101
0111 1111 1111 1110
0111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
1111 1111 1111 1111
1 LSB =
VREF
(GAIN x 65,536)
x 2
-32,768
-32,766
VREF/GAIN
V
REF
/GAIN
V
REF
/GAIN
Figure 21. ADC Bipolar Transfer Function
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MAX1135BCAP+T 功能描述:模数转换器 - ADC 16-Bit 150ksps 3.3V Single Supply RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
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