参数资料
型号: MAX11665AUT+T
厂商: Maxim Integrated Products
文件页数: 10/28页
文件大小: 0K
描述: ADC 12BIT 500KSPS 1CH SOT23-6
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 12
采样率(每秒): 500k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 696mW
电压电源: 模拟和数字
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-23-6
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
18 _____________________________________________________________________________________
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Pin Description
Pin Configurations
*CONNECT EP TO GROUND PLANE.
DEVICES DO NOT OPERATE WHEN EP IS NOT CONNECTED TO GROUND!
EP*
TOP VIEW
+
TOP VIEW
GND
SCLK
AIN
16
CS
5
DOUT
VDD
MAX11661
MAX11663
MAX11665
SOT23
2
34
+
MAX
29
DOUT
AIN2
110
SCLK
AIN1
OVDD
AGND
38
CHSEL
REF
7
CS
VDD
6
MAX11662
MAX11664
MAX11666
4
5
PIN
NAME
FUNCTION
MAX
SOT23
1
AIN1
Analog Input Channel 1. Single-ended analog input with respect to AGND with range of 0V to
VREF.
2
AIN2
Analog Input Channel 2. Single-ended analog input with respect to AGND with range of 0V to
VREF.
3
AIN
Analog Input Channel. Single-ended analog input with respect to GND with range of 0V to VDD.
2
GND
Ground. Connect GND to the GND ground plane.
3
AGND
Analog Ground. Connect AGND directly the GND ground plane.
4
REF
External Reference Input. REF defines the signal range of the input signal AIN1/AIN2: 0V to VREF.
The range of VREF is 1V to VDD. Bypass REF to AGND with 10FF || 0.1FF capacitor.
5
1
VDD
Positive Supply Voltage. Bypass VDD with a 10FF || 0.1FF capacitor to GND. VDD range is 2.2V
to 3.6V. For the SOT23 package, VDD also defines the signal range of the input signal AIN: 0V to
VDD.
6
CS
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a
conversion, and frames the serial-data transfer.
7
CHSEL
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for
conversion.
8
OVDD
Digital Interface Supply for SCLK, CS, DOUT, and CHSEL. The OVDD range is 1.5V to VDD.
Bypass OVDD with a 10FF || 0.1FF capacitor to GND.
9
5
DOUT
Three-State Serial-Data Output. ADC conversion results are clocked out on the falling edge of
SCLK, MSB first. See Figure 1.
10
4
SCLK
Serial-Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of
SCLK. See Figures 2 and 3.
EP
Exposed Pad (MAX Only). Connect EP directly to a solid ground plane. Devices do not operate
when EP is not connected to ground!
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