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参数资料
| 型号： | MAX11665AUT+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | ADC 12BIT 500KSPS 1CH SOT23-6 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 696mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
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24 _____________________________________________________________________________________
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Figure 13. Channel Select Timing Diagram
Dual-Channel Operation
The MAX11662/MAX11664/MAX11666 feature dual-input
channels. These devices use a channel-select (CHSEL)
input to select between analog input AIN1 (CHSEL = 0)
or AIN2 (CHSEL = 1). As shown in Figure 13, the CHSEL
signal is required to change between the 2nd and 12th
clock cycle within a regular conversion to guarantee
proper switching between channels.
14-Cycle Conversion Mode
The ICs can operate with 14 cycles per conversion.
Figure 14 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
mode. Also, observe that tACQ needs to be sufficiently
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for tACQ
requirements and the Analog Input section for a descrip-
tion of the analog inputs.
Applications Information
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the VDD
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the VDD, OVDD, and REF to ground with
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
Choosing an Input Amplifier
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
Figure 14. 14-Clock Cycle Operation
1
DATA CHANNEL AIN1
DATA CHANNEL AIN2
SCLK
CHSEL
DOUT
CS
23456
78
910111213141516
123456
78
910111213141516
1
DOUT
SCLK
(MSB)
SAMPLE
1/fSAMPLE
tACQ
tCONVERT
CS
23
4
D10
D11
56
78
910111213141
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX11665EVKIT# | 功能描述:数据转换 IC 开发工具 MAX11665 Eval Kit RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| MAX11666 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs |
| MAX11666AUB | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs |
| MAX11666AUB/V | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs |
| MAX11666AUB/V+ | 功能描述:模数转换器 - ADC 1-2Ch 12-Bit 500ksps ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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