参数资料
型号: MAX1400EAI+
厂商: Maxim Integrated Products
文件页数: 33/34页
文件大小: 0K
描述: IC ADC 18BIT LP 28-SSOP
产品培训模块: MAX11200 ADC
Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 46
位数: 18
采样率(每秒): 480
数据接口: QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 1.25mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 管件
输入数目和类型: 3 个差分,单极;3 个差分,双极;5 个伪差分,单极;5 个伪差分,双极
产品目录页面: 1396 (CN2011-ZH PDF)
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8
_______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX,
unless otherwise noted.) (Notes 19, 20, 21)
Note 19: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD).
Note 20: See Figure 4.
Note 21: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1400 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23: The MAX1400 is production tested with fCLKIN at 2.5MHz (1MHz for some IDD tests).
Note 24: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
Note 25: For read operations, SCLK active edge is falling edge of SCLK.
Note 26: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
CS Rising Edge to SCLK Rising
Edge Hold Time
t18
0
ns
SCLK High Pulse Width
t16
100
ns
SCLK Low Pulse Width
t17
100
ns
Data Valid to SCLK Rising Edge
Hold Time
t15
0
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t13
30
ns
Data Valid to SCLK Rising Edge
Setup Time
t14
30
ns
SCLK Setup to Falling Edge CS
t12
30
ns
CONDITIONS
SERIAL-INTERFACE WRITE OPERATION
800
A
at VDD = +5V
100
A
at VDD = +3.3V
100
A
at VDD = +3.3V
TO
OUTPUT
PIN
50pF
200
A
at VDD = +5V
Figure 1. Load Circuit for Bus Relinquish Time and VOL and
VOH Levels
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MAX1400EAI+T 功能描述:模数转换器 - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
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MAX1401CAI 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32