参数资料
型号: MAX1403EVKIT
厂商: Maxim Integrated Products
文件页数: 4/36页
文件大小: 0K
描述: EVAL KIT FOR MAX1403
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
ADC 的数量: 1
位数: 18
采样率(每秒): 480
数据接口: 串行
输入范围: ±VREF/增益
在以下条件下的电源(标准): 16.9mW @ 480SPS
工作温度: 0°C ~ 70°C
已用 IC / 零件: MAX1403
已供物品: 板,CD
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
12
______________________________________________________________________________________
Pin Description (continued)
NAME
FUNCTION
PIN
19
REFIN-
Negative Differential Reference Input. Bias REFIN- between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
20
REFIN+
Positive Differential Reference Input. Bias REFIN+ between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.
21
CALOFF-
Negative Offset Calibration Input. Used for system offset calibration. It forms the negative input of a fully
differential input pair with CALOFF+. Normally these inputs are connected to zero-reference voltages in
the system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
22
CALOFF+
Positive Offset Calibration Input. Used for system offset calibration. It forms the positive input of a fully
differential input pair with CALOFF-. Normally these inputs are connected to zero-reference voltages in the
system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.
23
DGND
Digital Ground. Reference point for digital circuitry.
24
VDD
Digital Supply Voltage (+2.7V to +3.6V)
25
INT
Interrupt Output. A logic low indicates that a new output word is available from the data register. INT
returns high upon completion of a full output word read operation. INT also returns high for short periods
(determined by the filter and clock control bits) if no data read has taken place. A logic high indicates
internal activity, and a read operation should not be attempted under this condition. INT can also provide
a strobe to indicate valid data at DOUT (MDOUT = 1).
26
DOUT
Serial Data Output. DOUT outputs data from the internal shift register containing information from the
Communications Register, Global Setup Registers, Transfer Function Registers, or Data Register. DOUT
can also provide the digital bit stream directly from the
Σ- modulator (MDOUT = 1).
27
DIN
Serial Data Input. Data on DIN is written to the input shift register and later transferred to the
Communications Register, Global Setup Registers, Special Function Register, or Transfer Function
Registers, depending on the register selection bits in the Communications Register.
28
SCLK
Serial Clock Input. Apply an external serial clock to transfer data to and from the MAX1403. This serial
clock can be continuous, with data transmitted in a train of pulses, or intermittently. If CS is used to frame
the data transfer, then SCLK may idle high or low between conversions and CS determines the desired
active clock edge (see Selecting Clock Polarity). If CS is tied permanently low, SCLK must idle high
between data transfers.
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