参数资料
型号: MAX1497EAI+T
厂商: Maxim Integrated Products
文件页数: 2/33页
文件大小: 0K
描述: IC ADC 3 1/2DIG W/LED DVR 28-SSO
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
位数: 3.5 位
采样率(每秒): 5
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
MAX1497/MAX1499
3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and C Interface
10
______________________________________________________________________________________
Pin Description
PIN
MAX1497
MAX1499
NAME
FUNCTION
131
VNEG
-2.5V Charge-Pump Voltage-Output. Connect a 0.1F capacitor to GND.
232
REF-
Negative Reference Voltage Input. For internal reference operation, connect REF- to
GND. For external reference operation, bypass REF- to GND with a 0.1F capacitor and
set VREF- from -2.2V to +2.2V, provided VREF+ > VREF-.
31
REF+
Positive Reference Voltage Input. For internal reference operation, connect a 4.7F
capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND
with a 0.1F capacitor and set VREF+ from -2.2V to +2.2V, provided VREF+ > VREF-.
42
AIN+
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND
with a 0.1F or greater capacitor.
53
AIN-
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1F or greater capacitor.
64
ISET
Segment Current Controller. Connect to ground through a resistor to set the segment
current. See Table 6 for segment current selection.
75
GND
Ground
8—
VDD
Analog and Digital Circuit Supply Voltage. Connect VDD to a +2.7V to +5.25V power
supply. Bypass VDD to GND with a 0.1F and a 4.7F capacitor.
98
CLK
External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock
input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK
register bit is reset to zero, the internal clock is used. Connect CLK to GND or DVDD
(MAX1499) or VDD (MAX1497) when the internal oscillator is used.
10
9
EOC
Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new
ADC result is available in the ADC result register.
11
10
CS
Active-Low Chip Select Input. Forcing CS low activates the serial interface.
12
11
DIN
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
13
12
SCLK
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK may idle high or low.
14
13
DOUT
Serial Data Output. DOUT presets serial data in response to register queries. Data shifts
out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
15
14
DIG0
Digit 0 Driver
16
15
DIG1
Digit 1 Driver
17
16
GLED
Ground for LED-Display Segment Driver
18
17
DIG2
Digit 2 Driver
19
18
DIG3
Digit 3 Driver
20
SEGA
Segment A Driver
21
SEGB
Segment B Driver
22
SEGC
Segment C Driver
23
SEGD
Segment D Driver
24
SEGE
Segment E Driver
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