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参数资料
| 型号： | MAX1497EAI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 30/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 3 1/2DIG W/LED DVR 28-SSO |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 位数： | 3.5 位 |
| 采样率（每秒）： | 5 |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
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MAX1497/MAX1499
3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and C Interface
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Notes 11, 12, Figure 8)
(AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference)
CREF+ = CREF- = 0.1F, CVNEG = 0.1F. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX.
Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Operating Frequency
fSCLK
0
4.2
MHz
SCLK Pulse-Width High
tCH
100
ns
SCLK Pulse-Width Low
tCL
100
ns
DIN to SCLK Setup
tDS
50
ns
DIN to SCLK Hold
tDH
0ns
CS Fall to SCLK Rise Setup
tCSS
50
ns
SCLK Rise to CS Rise Hold
tCSH
0ns
SCLK Fall to DOUT Valid
tDO
CLOAD = 50pF, Figures 13, 14
120
ns
CS Rise to DOUT Disable
tTR
CLOAD = 50pF, Figures 13, 14
120
ns
CS Fall to DOUT Enable
tDV
CLOAD = 50pF, Figures 13, 14
120
ns
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and
offset error.
Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Offset drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8: CLK and SCLK are disabled.
Note 9: LED drivers are disabled.
Note 10: Power-supply currents are measured with all digital inputs at either GND, DVDD, or VDD and with the device in internal-clock mode.
Note 11: All input signals are specified with tRISE = tFALL = 5ns (10% to 90% of DVDD) and are timed from a voltage level of 50% of
DVDD, unless otherwise noted.
Note 12: See the serial-interface timing diagrams.
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