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| 型号： | MAX15020ATP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 36 V |
| 输入电压： | 7.5 V ~ 40 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 300kHz ~ 500kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-TQFN-EP（5x5） |
2A, 40V Step-Down DC-DC Converter with
Dynamic Output-Voltage Programming
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
Δ V Q =
Δ I L
16 × C OUT × f SW
input capacitor must be carefully chosen to keep the
input-voltage ripple within design requirements. The
input-voltage ripple is comprised of Δ V Q (caused by the
capacitor discharge) and Δ V ESR (caused by the ESR
(equivalent series resistance) of the input capacitor).
The total voltage ripple is the sum of Δ V Q and Δ V ESR .
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
Δ V ESR = ESR × Δ I L
Normally, a good approximation of the output-voltage
ripple is Δ V RIPPLE ≈ Δ V ESR + Δ V Q . If using ceramic
capacitors, assume the contribution to the output-volt-
age ripple from ESR and the capacitor discharge to be
equal to 20% and 80%, respectively. Δ I L is the peak-to-
peak inductor current (see the Input Capacitor
? ? I OUT _ MAX + 2 ? ?
ESR =
C IN =
Δ V ESR
? Δ I L ?
I OUT _ MAX × D(1 ? D)
Δ V Q × f SW
Selection section) and f SW is the converter’s switching
frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
( V IN ? V OUT ) × V OUT
V IN SW × L
Δ I L =
D =
ESR =
C OUT = STEP RESPONSE
Δ V E S L × t STEP
where:
× f
V OUT
V IN
I OUT_MAX is the maximum output current, D is the duty
cycle, and f SW is the switching frequency.
The MAX15020 includes internal and external UVLO
hysteresis and soft-start to avoid possible unintentional
chattering during turn-on. However, use a bulk capaci-
tor if the input source impedance is high. Use enough
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during
transient loading.
Output Capacitor Selection
The allowable output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance and its ESR. The output
ripple is mainly composed of Δ V Q (caused by the
capacitor discharge) and Δ V ESR (caused by the volt-
age drop across the ESR of the output capacitor). The
equations for calculating the peak-to-peak output volt-
age ripple are:
greater duty cycle. The response time (t RESPONSE )
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitor ’s ESR, the drop
across the capacitor’s ESL ( Δ V ESL ), and the capacitor
discharge cause a voltage droop during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic and ceramic capacitors for better transient load
and voltage ripple performance. Surface-mount capaci-
tors and capacitors in parallel help reduce the ESL.
Keep the maximum output-voltage deviations below the
tolerable limits of the electronics powered. Use the fol-
lowing equations to calculate the required ESR, ESL,
and capacitance value during a load step:
V ESR
I STEP
I × t
Δ V Q
ESL =
I STEP
where I STEP is the load step, t STEP is the rise time of the
load step, and t RESPONSE is the response time of the
controller.
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| MAX15021ATI+ | 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Tracking/Seq RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
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