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参数资料
| 型号： | MAX15020ATP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 20TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 36 V |
| 输入电压： | 7.5 V ~ 40 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 300kHz ~ 500kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-TQFN-EP（5x5） |
2A, 40V Step-Down DC-DC Converter with
Dynamic Output-Voltage Programming
Compensation Design
The MAX15020 uses a voltage-mode control scheme
that regulates the output voltage by comparing the
error-amplifier output (COMP) with an internal ramp to
produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and
phase shift to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage error amplifi-
er. The power modulator has a DC gain set by V IN /
V RAMP , with a double pole and a single zero set by the
Compensation When f C < f ESR
Figure 3 shows the error-amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f ZESR occurs after f C .
f Z1 is set to 0.8 x f LC(MOD) and f Z2 is set to f LC to com-
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C OUT ) as described in the Inductor Selection and
Output Capacitor Selection sections.
Choose a value for the feedback resistor R9 in Figure 3
(values between 1k Ω and 10k Ω are adequate).
C12 is then calculated as:
output inductance (L), the output capacitance (C OUT )
(C6 in the Figure 2) and its ESR. The power modulator
incorporates a voltage feed-forward feature, which auto-
matically adjusts for variations in the input voltage
C 12 =
1
2 π × 0 . 8 × f LC × R 9
resulting in a DC gain of 9. The following equations
define the power modulator:
f C occurs between f Z2 and f P2 . The error-amplifier gain
(G EA ) at f C is due primarily to C11 and R9.
Therefore, G EA(fC) = 2 π x f C x C11 x R9 and the modu-
G MOD ( DC ) =
f LC =
V IN
V RAMP
1
2 π L × C
= 9
lator gain at f C is:
G MOD ( fC ) =
( 2 π )
G MOD ( DC )
2 × L × C OUT × f C 2
f ESR =
C 11 = C OUT
1
2 π × C OUT × E SR
The switching frequency is internally set at 300kHz or
500kHz, or can vary from 100kHz to 500kHz when driven
with an external SYNC signal. The crossover frequency
(f C ), which is the frequency when the closed-loop gain is
equal to unity, should be set as f SW / 2 π or lower.
Since G EA(fC) x G MOD(fC) = 1, C11 is calculated by:
f × L × C × 2 π
R 9 × G MOD ( DC )
f P2 is set at 1/2 the switching frequency (f SW ). R6 is
then calculated by:
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
R 6 =
1
2 π × C 11 × 0 . 5 × f SW
f Z 1 =
and f Z 2 =
R 7 =
ing a Type 3 compensator that introduces two zeros
and three poles into the control loop. The error amplifier
has a low-frequency pole (f P1 ) near the origin.
In reference to Figures 3 and 4, the two zeros are at:
1 1
2 π × R 9 × C 12 2 π × ( R 6 + R 7 ) × C 11
Since R7 >> R6, R7 + R6 can be approximated as R7.
R7 is then calculated as:
1
2 π × f LC × C 11
f P3 is set at 5 x f C . Therefore, C13 is calculated as:
f P 2 =
and f P 3 =
2 π × R 9 × ?
And the higher frequency poles are at:
1 1
2 π × R 6 × C 11 ? C12 × C13 ?
? C 12 + C 1 3 ? ?
C 13 =
C 12
2 π × C 12 × R 9 × f P 3 ? 1
14
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