参数资料
型号: MAX15022ATI+
厂商: Maxim Integrated
文件页数: 16/28页
文件大小: 0K
描述: IC REG QD BCK/LINEAR SYNC 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
拓扑: 降压(降压)同步(2),线性(LDO)(2)
功能: 任何功能
输出数: 4
频率 - 开关: 500kHz ~ 4MHz
电压/电流 - 输出 1: 0.6 V ~ 5.5 V,4A
电压/电流 - 输出 2: 0.6 V ~ 5.5 V,2A
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
? V ESR [mV]
I STEP [A] × t RESPONSE [ μ s ]
? V Q [V]
Use the following equation to calculate the input ripple
when only one regulator is enabled:
I CIN(RMS) [A] = I LOAD(MAX) [A] ×
V OUT_ [V] × ( V PVIN_ ? V OUT_ ) [V]
V PVIN_ [V]
The MAX15022 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use additional
bulk capacitance if the input source impedance is high. If
using a lower input voltage, additional input capacitance
put-voltage deviation below the tolerable limits of the
electronics being powered.
Use the following equations to calculate the required
output capacitance, ESR, and ESL for minimal output
deviation during a load step:
ESR [ m ? ] =
I STEP [A]
C OUT [ μ F ] =
helps to avoid possible undershoot below the undervolt-
age lockout threshold during transient loading.
ESL [ nH ] =
? V ESL [mV] × t STEP [ μ s ]
I STEP [A]
Output-Capacitor Selection
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of ? V Q (caused by
the capacitor discharge) and ? V ESR (caused by the
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
where I STEP is the load step, t STEP is the rise time of the
load step, and t RESPONSE is the response time of the
controller.
Compensation Design Guidelines
The MAX15022 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by
comparing the output voltage against a fixed reference.
The subsequent “error ” voltage that appears at the
C OUT [ μ F ] =
? I P ? P [A]
8 × ? V Q [V] × f SW [MHz]
error-amplifier output (COMP_) is compared against an
internal ramp voltage to generate the required duty
cycle of the PWM. A second order lowpass LC filter
ESR [ m ? ] =
2 × ? V ESR [mV]
? I P ? P [A]
removes the switching harmonics and passes the DC
component of the PWM signal to the output. The LC fil-
ter has an attenuation slope of -40dB/decade and intro-
where ? I P-P is the peak-to-peak inductor current, and
f SW is the switching frequency.
? V ESR and ? V Q are not directly additive since they are
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, ? V Q dominates. If
using electrolytic capacitors, ? V ESR dominates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with an
increased duty cycle. The response time (t RESPONSE )
depends on the gain bandwidth of the controller (see
the Compensation-Design Guidelines section). The
resistive drop across the output capacitor ’s ESR
( ? V ESR ), the drop across the capacitor’s ESL ( ? V ESL ),
and the capacitor discharge ( ? V Q ) causes a voltage
droop during the load-step (I STEP ). Use a combination
of low-ESR tantalum/aluminum electrolyte and ceramic
capacitors for better load transient and voltage ripple
performance. Non-leaded capacitors and capacitors in
parallel help reduce the ESL. Keep the maximum out-
duces 180° of phase shift at frequencies above the LC
resonant frequency. This phase shift in addition to the
inherent 180° of phase shift of the regulator’s negative
feedback system turns the feedback into unstable posi-
tive feedback. The error amplifier and its associated
circuitry must be designed to achieve a stable closed-
loop system.
The basic controller loop consists of a power modulator
(comprised of the regulator’s PWM, associated circuitry,
and LC filter), an output feedback divider, and an error
amplifier. The power modulator has a DC gain set by
V AVIN /V RAMP where the ramp voltage (V RAMP ) is a func-
tion of the V AVIN and results in a fixed DC gain of 4V/V,
providing effective feed-forward compensation of input-
voltage supply DC variations. The feed-forward com-
pensation eliminates the dependency of the power mod-
ulator’s gain on the input voltage such that the feedback
compensation of the error amplifier requires no modifi-
cations for nominal input-voltage changes. The output
filter is effectively modeled as a double-pole and a sin-
gle zero set by the output inductance (L), the DC resis-
tance of the inductor (DCR), the output capacitance
(C OUT ), and its equivalent series resistance (ESR).
16
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MAX15022ATI+ 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Dual LDO Ctlr RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5
MAX15022ATI+T 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Dual LDO Ctlr RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5
MAX15022EVKIT+ 功能描述:电源管理IC开发工具 MAX15022 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V
MAX15023ETG/V+ 功能描述:DC/DC 开关控制器 4.5-28V Input Dual Out Synch Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK
MAX15023ETG/V+T 功能描述:DC/DC 开关控制器 4.5-28V Input Dual Out Synch Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK