参数资料
型号: MAX15022ATI+
厂商: Maxim Integrated
文件页数: 9/28页
文件大小: 0K
描述: IC REG QD BCK/LINEAR SYNC 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
拓扑: 降压(降压)同步(2),线性(LDO)(2)
功能: 任何功能
输出数: 4
频率 - 开关: 500kHz ~ 4MHz
电压/电流 - 输出 1: 0.6 V ~ 5.5 V,4A
电压/电流 - 输出 2: 0.6 V ~ 5.5 V,2A
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Pin Description (continued)
PIN
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
B3
FB3
EN3
DVDD2
PGND2
LX2
PVIN2
EN4
FB4
B4
COMP2
FB2
EN2
SGND
AVIN
RT
EP
FUNCTION
Transconductance Amplifier Open-Drain Output for LDO Controller 3. Connect B3 to the base of an
external PNP transistor to regulate output 3.
Feedback Regulation Point for LDO Controller 3. Connect to the center tap of a resistive divider from the
output 3 to SGND to set the output voltage. The FB3 voltage regulates to 0.6V (typ).
LDO Enable Input for LDO Controller 3. EN3 must exceed 1.225V (typ) for the LDO controller to begin
regulating output 3.
Switch Driver Supply for Regulator 2. Connect externally to PVIN2.
Power Ground Connection for Regulator 2. Connect the negative terminals of the input and output filter
capacitors to PGND2. Connect PGND2 externally to SGND at a single point, typically at the negative
terminal of the input bypass capacitor.
Inductor Connection for Regulator 2. LX2 is the drain connection of the internal high-side p-channel
MOSFET and the drain connection of the internal synchronous n-channel MOSFET for Regulator 2.
Input Supply Voltage for Regulator 2. Connect to an external voltage source from 2.5V to 5.5V. Bypass
PVIN2 to PGND2 with a 1μF (min) ceramic capacitor.
LDO Enable Input for LDO Controller 4. EN4 must exceed 1.225V (typ) for the LDO controller to begin
regulating output 4.
Feedback Regulation Point for LDO Controller 4. Connect to the center tap of a resistive divider from
output 4 to SGND to set the output voltage. The FB4 voltage regulates to 0.6V (typ).
Transconductance Amplifier Open-Drain Output for LDO Controller 4. Connect B4 to the base of an
external PNP transistor to regulate output 4.
Error-Amplifier Output for Regulator 2. Connect COMP2 to the compensation feedback network.
Feedback Regulation Point for Regulator 2. Connect to the center tap of a resistive divider from the
regulator 2 output to SGND to set the output voltage. The FB2 voltage regulates to 0.6V (typ).
Enable Input for Regulator 2. When configured as a sequencer, EN2 must exceed 1.225V (typ) for the
PWM controller to begin regulating output 1. When configured as a tracker, connect EN2 to the center
tap of a resistive divider from the regulator 1 output.
Signal Ground. Connect SGND to PGND_ at a single point, typically near the negative terminal of the
input bypass capacitor.
Input Voltage. Bypass AVIN to SGND with a 100nF (min) ceramic capacitor.
Oscillator Timing Resistor Connection. Connect a 4.2k ? to 33k ? resistor from RT to SGND to program
the switching frequency from 500kHz to 4MHz.
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation.
Do not use as the main SGND connection.
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9
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