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| 型号： | MAX15022ATI+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 21/28页 |
| 文件大小： | 0K |
| 描述： | IC REG QD BCK/LINEAR SYNC 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 降压（降压）同步（2），线性（LDO）（2） |
| 功能： | 任何功能 |
| 输出数： | 4 |
| 频率 - 开关： | 500kHz ~ 4MHz |
| 电压/电流 - 输出 1： | 0.6 V ~ 5.5 V，4A |
| 电压/电流 - 输出 2： | 0.6 V ~ 5.5 V，2A |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
The locations of the zeros and poles should be such
Solving for C I :
that the phase margin peaks around f CO .
Set the ratios of f CO -to-f Z and f P -to-f CO equal to one anoth-
er, e.g., f CO = f P = 5 is a good number to get approximately
f Z f CO
C I [ pF] =
( 2 π × f CO [kHz] × L[ μ H] × C OUT [ μ F] )
4 × R F [k ? ]
f CO [kHz] ≤ SW
f LC [MHz] ≈
4) Place the compensator’s first zero f Z1 =
2 π × R F × C F
C F [ μ F] =
R I [k ? ] =
60° of phase margin at f CO . Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, f CO , at or below one-
tenth the switching frequency (f SW ):
f [kHz]
10
2) Calculate the LC double-pole frequency, f LC :
1
2 π × L[ μ H] × C OUT [ μ F]
where C OUT is the output capacitor of the regulator.
3) Select the feedback resistor, R F , in the range of
3.3k ? to 30k ? .
1
at or below the output filter’s dou-
ble-pole, f LC , as follows:
1
2 π × R F [k ? ] × 0.5 × f LC [kHz]
5) The gain of the modulator (Gain MOD )—comprised of
the regulator’s PWM, LC filter, feedback divider, and
6) For those situations where f LC < f CO < f ESR < f SW /2,
as with low-ESR tantalum capacitors, the compen-
sator’s second pole (f P2 ) should be used to cancel
f ESR . This provides additional phase margin. On the
system Bode plot, the loop gain maintains its
+20dB/decade slope up to 1/2 of the switching fre-
quency verses flattening out soon after the 0dB
crossover. Then set:
f P2 = f ESR
If a ceramic capacitor is used, then the capacitor ESR
zero, f ESR , is likely to be located even above 1/2 of the
switching frequency, that is f LC < f CO < f SW /2 < f ESR . In
this case, the frequency of the second pole (f P2 ) should
be placed high enough not to significantly erode the
phase margin at the crossover frequency. For example,
f P2 can be set at 5 x f CO , so that its contribution to phase
loss at the crossover frequency f CO is only about 11°:
f P2 = 5 x f CO
Once f P2 is known, calculate R I :
1
2 π × f P2 [kHz] × C I [ μ F]
7) Place the second zero (f Z2 ) at 0.2 x f CO or at f LC ,
whichever is lower, and calculate R 1 using the fol-
lowing equation:
Gain MOD = 4 ×
(2 π × f CO [MHz]) × L[ μ H] × C OUT [ μ F]
associated circuitry—at the crossover frequency is:
1
2
R 1 [k ? ] =
1
2 π × f Z2 [kHz] × C I [ μ F]
The gain of the error amplifier (Gain E/A ) in midband fre-
quencies is:
8) Place the third pole (f P3 ) at 1/2 the switching fre-
quency and calculate C CF from:
Gain E/A = 2 π × f CO [kHz] × C I [ μ F] × R F [k ? ]
The total loop gain is the product of the modulator gain
C CF [ n F] =
( 2 π × 0.5 × f SW [MHz] × R F [k ? ] )
1
and the error amplifier gain at f CO should be equal to 1,
as follows:
9) Calculate R 2 as:
(2 π × f CO [kHz]) × C OUT [ μ F] × L[ μ H]
So:
4 ×
Gain MOD x Gain E/A = 1
1
2
R 2 [k ? ] = R 1 [k ? ] ×
where V FB = 0.6V (typ).
V FB [V]
V OUT_ [V] ? V FB [V]
× 2 π × f CO [kHz] × C I [ p F] × R F [k ? ] = 1
______________________________________________________________________________________
21
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