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| 型号： | MAX15022ATI+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC REG QD BCK/LINEAR SYNC 28TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 降压（降压）同步（2），线性（LDO）（2） |
| 功能： | 任何功能 |
| 输出数： | 4 |
| 频率 - 开关： | 500kHz ~ 4MHz |
| 电压/电流 - 输出 1： | 0.6 V ~ 5.5 V，4A |
| 电压/电流 - 输出 2： | 0.6 V ~ 5.5 V，2A |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 是 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
LDO Controllers
Design Procedure
PNP Pass Transistors Selection
The pass transistors must meet specifications for current
gain (?), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
Stability Requirements
The MAX15022’s B3 and B4 outputs are designed to
drive bipolar PNP transistors. These PNP transistors
form linear regulators with positive outputs. An internal
transconductance amplifier drives the external pass
transistors. The transconductance amplifier, pass tran-
sistor’s specifications, the base-emitter resistor, and the
output capacitor determine the loop stability.
I OUT3/4 [A] = ? I B3/4(MIN) [A] ?
?
?
V BE [V] ?
R PULL [ ? ] ? ?
× β
The total DC loop gain (A V ) is the product of the gains of
the internal transconductance amplifier, the gain from
base to collector of the pass transistor, and the attenua-
tion of the feedback divider. The transconductance ampli-
g C_ × ? IN P1/2 ?
R IN [ k ? ] = β x ? ?
A P m ? PNP × ? OUT3/4 1FB3/4 2FB3/4 ?
×
where I B3/4(MIN) is the minimum base-drive current and
R PULL is the pullup resistor connected between the
transistor’s base and emitter.
In addition, to avoid premature dropout, V CE-SAT must
be less than or equal to (V PVIN_(MIN) - V OUT3/4 ).
Furthermore, the transistor’s current gain increases the
linear regulator ’s DC loop gain (see the Stability
Requirements section), so excessive gain destabilizes
the output. Therefore, transistors with high current gain
at the maximum output current, such as Darlington
transistors, are not recommended. The transistor ’s
input capacitance and input resistance also create a
second pole, which could be low enough to destabilize
the LDO when the output is heavily loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output volt-
age differential that the linear regulator supports.
Alternately, the package’s power dissipation could limit
the useable maximum input-to-output voltage differential.
The maximum power-dissipation capability of the tran-
sistor’s package and mounting must support the actual
power dissipation in the device without exceeding the
fier regulates the output voltage by controlling the pass
transistor’s base current. Its DC gain is approximately:
? R × R ?
? R IN + R P1/2 ?
where g C_ is the transconductance of the internal
amplifier and is typically 1.2mA/mV, R P1/2 is the resistor
across the base and the emitter of the pass transistor in
k ? , and R IN is the input resistance of the pass transis-
tor, and can be calculated by:
? 26[mV] ?
? I OUT3/4 [ μ A ] ?
The DC gain for the pass transistor (A P ), including the
feedback divider, is approximately:
? R × (R + R ) ?
= g
? R OUT3/4 + R 1FB3/4 + R 2FB3/4 ?
R 2FB3/4
R 1FB3/4 + R 2F B 3/4
I [ mA ]
26 [ mV ]
maximum junction temperature. The power dissipated
equals the maximum load current multiplied by the
maximum input-to-output voltage differential.
where g m ? PNP = OUT3/4
.
A V C_ × ? IN P1/2 ? × A P
+ R
R 1FB3/4 [ k ? ] = R 2FB3/4 [ k ? ] ? OUT3/4
? 1 ?
f POLE1 [kHz] =
=
Output 3 and Output 4 Voltage Selection
The MAX15022 positive linear-regulator output voltage
is set with a resistive divider from the desired output
(V OUT3/4 ) to FB3/4 to SGND (see Figures 7 and 8).
First, select the R 2FB3/4 resistance value (below 30k ? ).
Then, solve for R 1FB3/4 :
? V [V] ?
? V FB3/4 [V] ?
where V OUT3/4 can support output voltages as low as
0.6V and V FB3/4 is 0.6V (typ).
The total DC loop gain for output 3 and output 4 is:
? R × R ?
= g
? R IN P1/2 ?
The output capacitance (C OUT_ ) and the load resis-
tance (R OUT_ ) create a dominant pole (f POLE1 ) at:
1
2 π × C OUT3/4 [ μ F ] × R OUT3/4 [ k ? ]
I OUT3/4(MAX) [mA]
2 π × C OUT3/4 [ μ F ] × V OUT3/4 [V]
22
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