参数资料
型号: MAX15023EVKIT+
厂商: Maxim Integrated Products
文件页数: 20/28页
文件大小: 0K
描述: KIT EVALUATION FOR MAX15023 CTLR
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 2,非隔离
输出电压: 1.2V,3.3V
电流 - 输出: 10A,5A
输入电压: 9 ~ 16 V
稳压器拓扑结构: 降压
频率 - 开关: 500kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX15023
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
It is recommended to have a phase margin around
+50° to +60° to maintain a robust loop stability and
well-behaved transient response.
If an electrolytic or large-ESR tantalum output capacitor
is used, the capacitor ESR zero f ZO typically occurs
The total loop gain as the product of the modulator gain
and the error amplifier gain at f O should equal 1. So:
Gain MOD × Gain EA = 1
Therefore:
×
between the LC poles and the crossover frequency f O
(f PO < f ZO < f O ). In this case, use a Type II (PI or pro-
portional-integral) compensation network.
V IN ESR
V OSC ( 2 π × f O × L OUT )
×
V FB
V OUT
× g m × R F = 1
If a ceramic or low-ESR tantalum output capacitor is
used, the capacitor ESR zero typically occurs above
the desired crossover frequency f O , that is f PO < f O <
f ZO . In this situation, choose a Type III (PID or propor-
tional-integral-derivative) compensation network.
Solving for R F :
R F =
V OSC × ( 2 π × f O × L OUT ) × V OUT
V FB × V IN × g m × ESR
Type II Compensation Network
(See Figure 4)
2) Set a midband zero (f Z1 ) at 0.75 x f PO (to cancel
one of the LC poles):
If f ZO is lower than f O and close to f PO , the phase lead
of the capacitor ESR zero almost cancels the phase
loss of one of the complex poles of the LC filter around
the crossover frequency. Therefore, a Type II compen-
sation network with a midband zero and a high-fre-
f Z 1 =
Solving for C F :
1
2 π × R F × C F
= 0 . 75 × f PO
quency pole can be used to stabilize the loop. In Figure
4, R F and C F introduce a midband zero (f Z1 ). R F and
C CF in the Type II compensation network also provide a
high-frequency pole (f P1 ), which mitigates the effects of
C F =
1
2 π × R F × f PO × 0 . 75
the output high-frequency ripple.
To calculate the component values for Type II compen-
sation network in Figure 4, follow the instruction below:
3) Place a high-frequency pole at f P1 = 0.5 x f SW (to
attenuate the ripple at the switching frequency, f SW )
and calculate C CF using the following equation:
1) Calculate the gain of the modulator (Gain MOD )—
composed of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:
C CF =
1
π × R F × f SW ?
1
C F
×
Gain MOD =
V IN ESR
V OSC ( 2 π × f O × L OUT )
×
V FB
V OUT
V OUT
R 1
where V IN is the regulator’s input voltage, V OSC is the
amplitude of the ramp in the pulse-width modulator,
V FB is the FB_ input voltage set-point (0.6V typically,
see Electrical Characteristics table), and V OUT is the
desired output voltage.
The gain of the error amplifier (Gain EA ) in midband fre-
quencies is:
R 2
V REF
g m
R F
C F
COMP
C CF
Gain EA = g m × R F
where g m is the transconductance of the error amplifier.
Figure 4. Type II Compensation Network
20
Maxim Integrated
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