参数资料
型号: MAX15026CATD+T
厂商: Maxim Integrated Products
文件页数: 17/23页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 14TDFN
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 2.4MHz
占空比: 88%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
The gain of the error amplifier (GAIN EA ) in midband fre-
quencies is:
5) Place the third pole (f P3 ) at 1/2 the switching fre-
quency and calculate C CF :
GAIN EA = 2 π x f O x C 1 x R F
The total loop gain as the product of the modulator gain
and the error amplifier gain at f O is 1.
C CF =
C F
( 2 π × 0 . 5 × f SW × R F × C F ) ? 1
GAIN MOD × GAIN EA = 1
6) Calculate R 2 as:
× R 1
So:
V IN
V RAMP
×
1
( 2 π × f O ) 2 × C OUT × L OUT
R 2 =
V FB
V OUT ? V FB
MOSFET Selection
× ( 2 π × f × L × C
C I = RAMP O OUT OUT
Solving for C I :
V
V IN × R F
)
The MAX15026 step-down controller drives two external
logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:
? On-Resistance (R DS(ON) )
3) Use the second pole (f P2 ) to cancel f ZO when f PO <
f O < f ZO < f SW /2. The frequency response of the
loop gain does not flatten out soon after the 0dB
crossover, and maintains a -20dB/decade slope up
to 1/2 of the switching frequency. This is likely to
occur if the output capacitor is a low-ESR tantalum.
Set f P2 = f ZO .
When using a ceramic capacitor, the capacitor ESR
zero f ZO is likely to be located even above 1/2 the
switching frequency, f PO < f O < f SW /2 < f ZO . In this
case, place the frequency of the second pole (f P2 ) high
enough to not significantly erode the phase margin at
the crossover frequency. For example, set f P2 at 5 x f O
so that the contribution to phase loss at the crossover
frequency f O is only about 11°:
f P2 = 5 x f PO
Once f P2 is known, calculate R I:
? Maximum Drain-to-Source Voltage (V DS(MAX) )
? Minimum Threshold Voltage (V TH(MIN) )
? Total Gate Charge (Q G )
? Reverse Transfer Capacitance (C RSS )
? Power Dissipation
The two n-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at V GS =
4.5V. For maximum efficiency, choose a high-side
MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure
that the conduction losses at minimum input voltage do
not exceed the MOSFET package thermal limits, or vio-
late the overall thermal budget. Also, ensure that the
conduction losses plus switching losses at the maxi-
mum input voltage do not exceed package ratings or
violate the overall thermal budget. Ensure that the DL
gate driver can drive the low-side MOSFET. In particu-
lar, check that the dv/dt caused by the high-side
R I =
1
2 π × f P 2 × C I
MOSFET turning on does not pull up the low-side
MOSFET gate through the drain-to-gate capacitance
of the low-side MOSFET, which is the most frequent
4) Place the second zero (f Z2 ) at 0.2 x f O or at f PO ,
whichever is lower, and calculate R 1 using the fol-
lowing equation:
cause of cross-conduction problems.
Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs
with low gate charge so that V CC can power both dri-
R 1 =
1
2 π × f Z 2 × C I
? R I
vers without overheating the device.
P DRIVE = V CC x Q G_TOTAL x f SW
where Q G_TOTAL is the sum of the gate charges of the
two external MOSFETs.
Maxim Integrated
17
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