参数资料
型号: MAX15026CATD+T
厂商: Maxim Integrated Products
文件页数: 7/23页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 14TDFN
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 2.4MHz
占空比: 88%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 14-WFDFN 裸露焊盘
包装: 带卷 (TR)
MAX15026
Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Maxim Integrated
NAME
IN
V CC
PGOOD
EN
LIM
COMP
FB
RT
GND
DRV
DL
BST
LX
DH
EP
FUNCTION
Regulator Input. Bypass IN to GND with a 1μF minimum ceramic capacitor. Connect IN to V CC when
operating in the 5V ±10% range.
5.25V Linear Regulator Output. Bypass V CC to GND with a minimum of 4.7μF low-ESR ceramic
capacitor to ensure stability up to the regulated rated current when V CC supplies the drive current at
DRV. Bypass V CC to GND when V CC supplies the device core quiescent current with a 2.2μF
minimum ceramic capacitor.
Open-Drain Power-Good Output. Connect PGOOD with an external resistor to any supply voltage.
Active-High Enable Input. Pull EN to GND to disable the output. Connect EN to V CC for always-on
operation. EN can be used for power sequencing and as a UVLO adjustment input.
Current-Limit Adjustment. Connect a resistor from LIM to GND to adjust current-limit threshold from
30mV (R LIM = 6k ? ) to 300mV (R LIM = 60k ? ). See the Setting the Valley Current Limit section.
Compensation Input. Connect compensation network from COMP to FB or from COMP to GND. See
the Compensation section.
Feedback Input. Connect FB to a resistive divider between output and GND to adjust the output
voltage between 0.6V and (0.85 x Input Voltage). See the Setting the Output Voltage section.
Oscillator Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency
from 200kHz to 2MHz. See the Setting the Switching Frequency section.
Ground
Drive Supply Voltage. DRV is internally connected to the anode terminal of the internal boost diode.
Bypass DRV to GND with a 2.2μF minimum ceramic capacitor (see the Typical Application Circuits ).
Low-Side Gate-Driver Output. DL swings from DRV to GND. DL is low during UVLO.
Boost Flying Capacitor. Connect a ceramic capacitor with a minimum value of 100nF between BST
and LX.
External Inductor Connection. Connect LX to the switching side of the inductor. LX serves as the
lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage
drop of the synchronous MOSFET.
High-Side Gate-Driver Output. DH swings from LX to BST. DH is low during UVLO.
Exposed Pad. Internally connected to GND. Connect EP to a large copper plane at GND potential to
improve thermal dissipation. Do not use EP as the only GND ground connection.
7
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