参数资料
型号: MAX15039ETG+T
厂商: Maxim Integrated Products
文件页数: 16/19页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 6A 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 4.95 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-TQFN-EP(4x4)
6A, 2MHz Step-Down Regulator
with Integrated Switches
R 2 =
C O x ESR
C 3
Table 2. Mode Selection
MODE CONNECTION OPERATION MODE
C 2 =
Set the third compensation pole at 1/2 of the switching
frequency. Calculate C2 as follows:
1
π × R 1 × f S
The above equations provide application compensation
when the zero-cross frequency is significantly higher than
the double-pole frequency. When the zero-cross frequen-
cy is near the double-pole frequency, the actual zero-
GND
Unconnected or
V DD /2
V DD
Forced PWM
Forced PWM. Soft-start up into a
prebiased output (monotonic startup).
Skip Mode. Soft-start into a prebiased
output (monotonic startup).
cross frequency is higher than the calculated frequency.
In this case, lowering the value of R1 reduces the zero-
cross frequency. Also, set the third pole of the type III
compensation close to the switching frequency if the
zero-cross frequency is above 200kHz to boost the phase
margin. The recommended range for R3 is 2k Ω to 10k Ω .
Note that the loop compensation remains unchanged if
only R4’s resistance is altered to set different outputs.
MODE Selection
GAIN (dB)
COMPENSATION
TRANSFER
FUNCTION
DOUBLE POLE
POWER-STAGE
TRANSFER
FUNCTION
OPEN-LOOP
GAIN
THIRD
POLE
SECOND
POLE
The MAX15039 features a mode selection input
(MODE) that users can select a functional mode for the
device (see Table 2).
Forced-PWM Mode
Connect MODE to GND to select forced-PWM mode. In
forced-PWM mode, the MAX15039 operates at a con-
stant switching frequency (set by the resistor at FREQ
terminal) with no pulse skipping. PWM operation starts
after a brief settling time when EN goes high. The low-
side switch turns on first, charging the bootstrap
capacitor to provide the gate-drive voltage for the high-
side switch. The low-side switch turns off either at the
end of the clock period or once the low-side switch
sinks 1.35A current (typ), whichever occurs first. If the
low-side switch is turned off before the end of the clock
period, the high-side switch is turned on for the remain-
ing part of the time interval until the inductor current
reaches 0.9A, or the end of clock cycle is encountered.
Starting from the first PWM activity, the sink current
threshold is increased through an internal 4-step DAC
to reach the current limit of 11A after 128 clock periods.
This is done to help a smooth recovery of the regulated
voltage even in case of accidental prebiased output in
spite of the initial forced-PWM mode selection.
FIRST AND SECOND ZEROS
Figure 4. Type III Compensation Illustration
Soft-Starting Into a Prebiased Output
Mode (Monotonic Startup)
When MODE is left unconnected or biased to V DD /2, the
MAX15039 soft-starts into a prebiased output without dis-
charging the output capacitor. This type of operation is
also termed monotonic startup. See the Starting Into
Prebiased Output waveforms in the Typical Operating
Characteristics section for an example.
In monotonic startup mode, both low-side and high-
side switches remain off to avoid discharging the prebi-
ased output. PWM operation starts when the FB voltage
crosses the SS voltage. As in forced-PWM mode, the
PWM activity starts with the low-side switch turning on
first to build the bootstrap capacitor charge.
16
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