参数资料
型号: MAX15041ETE+T
厂商: Maxim Integrated Products
文件页数: 13/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 16TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 25.2 V
输入电压: 4.5 V ~ 28 V
PWM 型: 电流模式
频率 - 开关: 350kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-TQFN-EP(3x3)
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
FEEDBACK
DIVIDER
V OUT
ERROR AMPLIFIER
POWER MODULATOR
COMPENSATION
V IN
RAMP
OUTPUT FILTER
AND LOAD
R 1
FB
Σ
g MC
COMP
Q HS
V OUT
R 2
CONTROL
LOGIC
L0
DCR
g MV
R OUT
R C
*C CC
PWM
COMPARATOR
Q LS
I L
ESR
R LOAD
C OUT
C C
V COMP
G MOD
V OUT
I L
R OUT = A VEA /g MV
NOTE: THE G MOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
REF
*C CC IS OPTIONAL.
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
Figure 1. Peak Current-Mode Regulator Transfer Model
R OUT × ( sC C R C + 1 )
?? s ( C C + C CC ) ( R C + R OUT ) + 1 ?? × ?? s ( C C || C CC )( R C || R OUT ) + 1 ??
( sC O U T ESR + 1 )
?? sC OUT ( ESR + R LOAD ) + 1 ??
× × α × β
Gain =
f P 1 =
f P 2 =
f P 3 =
f Z 1 =
f Z 2 =
V FB ( sC C R C + 1 )
? ? + 1 ? × ( sC CC R C + 1 )
? sC C ?
( sC OUT ESR + 1 )
?? s C OUT ( ESR + R LOAD ) + 1 ??
Having defined the power modulator’s transfer function
gain, the total system loop gain can be written as fol-
lows (see Figure 1):
α=
β = G MOD × R LOAD ×
R 2 A VEA
R 1 + R 2 R OUT
where R OUT is the quotient of the error amplifier’s DC
gain, A VEA , divided by the error amplifier’s transcon-
ductance, g MV ; R OUT is much larger than R C and C C is
much larger than C CC .
Rewriting:
Gain = A VEA ×
V OUT ? ? A VEA ? ?
? ? g MV ?
× G MOD R LOAD ×
The dominate poles and zeros of the transfer loop gain
is shown below:
g MV 1
2 π × 10 A VEA [ dB ] / 20 × C C 2 π × C OUT ( ESR + R LOAD )
1 1
2 π × C CC R C 2 π × C C R C
1
2 π × C OUT ESR
The order of pole-zero occurrence is:
f P 1 < f P 2 < f Z 1 < f Z 2 ≤ f P 3
Note under heavy load, f P2 , may approach f Z1 .
A graphical representation of the asymptotic system
closed-loop response, including the dominant pole and
zero locations is shown in Figure 2.
______________________________________________________________________________________
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