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| 型号： | MAX15118EWI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/23页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 18A 28WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.17 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 18A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFBGA，WLBGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 28-WLP（3.5x2） |
MAX15118
High-Efficiency, 18A, Current-Mode Synchronous
Step-Down Regulator with Integrated Switches
? I P ? P
V RIPPLE(C) =
C OUT =
Output Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output-ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL as follows:
V
V RIPPLE = RIPPLE(C) + V RIPPLE(ESR) + V RIPPLE(ESL)
where the output ripple due to output capacitance, ESR,
and ESL is:
P ? I
8 × C OUT × f SW
V RIPPLE(ESR) = ? P × ESR
and V RIPPLE(ESL ) can be approximated as an inductive
divider from LX to GND:
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
instantly changes by ESR x ?I LOAD . Before the controller
can respond, the output deviates further, depending on
the inductor and output capacitor values. After a short
time, the controller responds by regulating the output
voltage back to the predetermined value.
Use higher C OUT values for applications that require
light-load operation or transition between heavy load and
light load, triggering skip mode, causing output under-
shooting or overshooting. When applying the load, limit
the output undershooting by sizing C OUT according to
the following formula:
? I LOAD
3f CO × ? V OUT
where ?IL OAD is the total load change, f CO is the unity-
gain bandwidth (or zero-crossing frequency), and ?V OUT
is the desired output undershooting. When removing the
load and entering skip mode, the device cannot control
output overshooting, since it has no sink current capabil-
= V IN ×
V RIPPLE (ESL) = V LX ×
ESL ESL
L L
ity; see the Skip Mode Frequency and Output Ripple
section to properly size C OUT under this circumstance.
( V IN OUT ) × ?
? V OUT ?
? I P ? P =
( ) , voltage soar (overshoot)
C OUT (MIN) =
( V FIN + V SOAR )
? V INIT
where V LX swings from V IN to GND.
The peak-to-peak inductor current ( D I P-P ) is:
? V ?
? V IN ?
L × f SW
When using ceramic capacitors, which generally have
A worst-case analysis in sizing the minimum output
capacitance takes the total energy stored in the inductor
into account, as well as the allowable sag/soar (under-
shoot/overshoot) voltage as follows:
L × I 2 OUT ( MAX ) ? I 2 OUT ( MIN )
2 2
V INIT ? ( V FIN ? V SAG )
low-ESR, D V RIPPLE(C) dominates. When using electro-
lytic capacitors, D V RIPPLE(ESR) dominates. Use ceramic
capacitors for low ESR and low ESL at the switching fre-
quency of the converter. The ripple voltage due to ESL is
C OUT(MIN) =
L × ( I 2 OUT ( MAX ) ? I 2 OUT ( MIN )
2 2
) , voltage sag (undershoot)
negligible when using ceramic capacitors.
As a general rule, a smaller inductor ripple-current results
in less output-ripple voltage. Since inductor-ripple cur-
rent depends on the inductor value and input voltage, the
output-ripple voltage decreases with larger inductance
and increases with higher input voltages. However, the
inductor-ripple current also impacts transient-response
performance, especially at low V IN to V OUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step.
where I OUT(MAX) and I OUT(MIN) are the initial and final
values of the load current during the worst-case load
dump, V INIT is the initial voltage prior to the transient,
V FIN is the steady-state voltage after the transient, V SOAR
is the allowed voltage soar (overshoot) above V FIN , and
V SAG is the allowable voltage sag below V FIN . The terms
(V FIN + V SOAR ) and (V FIN - V SAG ) represent the maxi-
mum/minimum transient output voltage reached during
the transient, respectively.
Use these equations for initial output-capacitor selection.
Determine final values by testing a prototype or an evalu-
ation circuit under the worst-case conditions.
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