参数资料
型号: MAX1513ETP+T
厂商: Maxim Integrated Products
文件页数: 22/28页
文件大小: 0K
描述: IC CNTRLR TFT-LCD PS 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 1
输出电压: 2.7 V ~ 50 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
TFT-LCD Power-Supply Controllers
A DC =
×
×
The DC loop gain (A DC ) is approximately:
R 2 1 - D
R 1 + R 2 0 . 554 × R CS
V MAIN
I MAIN ( EFF )
C OUT ( MIN ) =
10 × A DC × I MAIN(EFF)
2 π × f Z × V MAIN
where f Z is the frequency of the RHP zero and the
where R1 and R2 are the feedback-divider resistors
(Figure 1), D is the duty cycle, I MAIN(EFF) is the effec-
tive maximum output current as described in the
Inductor Selection section, 0.554 is the gain of the cur-
rent-sense amplifier, and R CS is the equivalent sense-
resistor value given by:
R CS = SF × R L ( TYP )
where R L(TYP) is the typical value of the inductor DCR,
and SF is either 1 or the scale factor in step 5 of the
Current-Sense Network Selection section.
ESR zero.
Using the typical operating circuit in Figure 1 as an
example: the duty cycle is 0.67, the effective maximum
output current is 500mA, the inductor is 2.2μH with a
typical DCR of 24m ? , and the output capacitor is 10μF
with a maximum ESR of 20m ? . The scale factor for the
current-sense network is 1, so R CS is 24m ? . The DC
loop gain A DC is 62, the RHP zero is at 236kHz, and the
ESR zero is at 796kHz. Since the frequency of the ESR
zero is higher than that of the RHP zero, the unity-gain
crossover frequency should be determined based on
the RHP zero. The minimum output capacitance for sta-
ble operation is:
f P ( DOMINANT ) =
The frequency of the dominant pole is:
I MAIN ( EFF )
2 π × V MAIN × C OUT
C OUT ( MIN ) =
5 × 62 × 500 mA
2 π × 236 kHz × 15 V
≈ 6 . 97 μ F
The frequency of the RHP zero is:
Lead or lag compensation can be useful to compen-
sate for particular component choices or to optimize
f Z ( RHP ) = ( 1 - D )
2
×
V MAIN
2 π × L × I MAIN ( EFF )
the transient response for various output capacitor or
inductor values.
f Z ( ESR ) =
The frequency of the ESR zero is:
1
2 π × R ESR × C OUT
The unity-gain crossover frequency is:
f CROSSOVER = A DC × f P ( DOMINANT )
For stable operation, select an output capacitor with
enough capacitance and a low enough ESR to ensure
that the dominant pole is low enough so the loop gain
reaches unity well before either the ESR zero or the
Adding lead compensation (the R3/C1 network from
V MAIN to FB in Figure 11) increases the loop band-
width, which can increase the speed of response to
transients. Too much speed can destabilize the loop
and is not needed or recommended for Figure 1’s com-
ponents. Lead compensation adds a zero-pole pair,
providing gain at higher frequencies and increasing
loop bandwidth. The frequencies of the zero and pole
for lead compensation depend on the feedback-divider
resistors and the RC network between V MAIN and FB.
The frequencies of the zero and pole for the lead com-
pensation are:
RHP zero, the lower of which should preferably occur at
or above 5 times the unity-gain frequency as long as
the two zeros are well separated. Calculate the mini-
f Z _ LEAD =
1
2 π × ( R 1 + R 3 ) × C 1
5 × A DC × I MAIN ( EFF )
[
]
2 π × ? R 3 +
? × C 1
mum output capacitance for stable operation using:
C OUT ( MIN ) =
2 π × min f Z ( RHP ) , f Z ( ESR ) × V MAIN
f P _ LEAD =
?
?
1
R1 × R2 ?
R 1 + R 2 ?
If the RHP zero and the ESR zero occur simultaneously,
place the dominant pole so that the unity-gain frequen-
cy is less than 1/10th the frequency of the zeros.
Calculate the minimum output capacitance for stable
operation using:
At high frequencies, R3 is effectively in parallel with R1,
determining the amount of added high-frequency gain.
If R3 is very large, there is no added gain and as R3
approaches zero, the added gain approaches the
inverse of the feedback-divider’s attenuation. A typical
value for R3 is greater than 1/2 of R1. The value of C1
22
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