参数资料
型号: MAX1513ETP+T
厂商: Maxim Integrated Products
文件页数: 26/28页
文件大小: 0K
描述: IC CNTRLR TFT-LCD PS 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 1
输出电压: 2.7 V ~ 50 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
TFT-LCD Power-Supply Controllers
? I BIAS FE ? ?
× h
A V _ LR ≈ ? V T ? × ? 1 + ? I ? ? × V REF
where C IN =
, R IN =
g m h FE
2 π f T
? 4 ? ?
? ?
? ? LOAD _ LR ? ?
where V T is 26mV at room temperature and I BIAS is the
current through the base-to-emitter resistor (R BE ). Each
of the four linear-regulator controllers is designed for a
different maximum output current, so they have differ-
ent output drive currents and different bias currents
,
g m
g m is the transconductance of the pass transistor,
and f T is the transition frequency. Both parameters
can be found in the transistor’s data sheet. Because
R BE is much greater than R IN , the above equation
can be simplified:
(I BIAS ). Each controller’s bias current can be found in
the Electrical Characteristics table. The current listed in
the conditions column for the FB_ regulation voltage
f POLE _ IN =
1
2 π × C IN × R IN
specification is the individual controller’s bias current.
The base-to-emitter resistor for each controller should
The equation can be further simplified:
R BE =
f POLE _ IN =
be chosen to set the correct I BIAS :
V BE
I BIAS
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
4)
f T
h FE
Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FB_ and GND (including stray capacitance):
2 π × C FB ( UPPER LOWER
amplifier delay, the pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system. The output capacitor’s
f POLE _ FB =
× R || R
1
)
ESR generates a zero. For proper operation, use the
following equations to verify the linear regulator is prop-
erly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
5)
where C FB is the capacitance between FB_ and
ground, R UPPER is the upper resistor of the linear
regulator’s feedback divider, and R LOWER is the
lower resistor of the divider.
Next, calculate the zero caused by the output
capacitor’s ESR:
f POLE _ LR =
I LOAD ( MAX )_ LR
2 π × C OUT _ LR × V OUT _ LR
f POLE _ ESR =
1
2 π × C OUT _ LR × R ESR
The unity-gain crossover of the linear regulator is:
where R ESR is the equivalent series resistance
f CROSSOVER = A V _ LR × f POLE _ LR
6)
of C OUT_LR .
To ensure stability, choose C OUT_LR large enough
2)
3)
The pole created by the internal amplifier delay is
about 1MHz:
f POLE _ AMP ≈ 1 MHz
Next, calculate the pole set by the transistor’s input
capacitance C IN , the transistor’s input resistance
R IN , and the base-to-emitter pullup resistor:
so the crossover occurs well before the poles and
zero calculated in steps 2 to 5. The poles in steps 3
and 4 generally occur at several megahertz and
using ceramic capacitors ensures the ESR zero
occurs at several megahertz as well. Placing the
crossover below 500kHz is sufficient to avoid the
amplifier-delay pole and generally works well,
unless unusual component choices or extra capac-
itances move the other poles or zero below 1MHz.
f POLE _ IN =
1
2 π × C IN × ( R BE || R IN
)
26
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