参数资料
型号: MAX1513ETP+T
厂商: Maxim Integrated Products
文件页数: 8/28页
文件大小: 0K
描述: IC CNTRLR TFT-LCD PS 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 1
输出电压: 2.7 V ~ 50 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
TFT-LCD Power-Supply Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V IN = 5V, V MAIN = 15V, V GON = 25V, V GOFF = -10V, V LOGIC = 3.3V, V GAMMA = 14.7V, T A = +25°C, unless other-
wise noted.)
BUFFER-AMPLIFIER LARGE-SIGNAL
STEP RESPONSE
MAX1513/14 toc10
BUFFER-AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX1513/14 toc11
V OUTB
1V/div
1 μ s/div
V FBPB
5V/div
AC-COUPLED
V OUTB
5V/div
AC-COUPLED
1 μ s/div
AC-COUPLED
I OUTB
50mA/div
0mA
Pin Description
PIN
NAME
MAX1513 MAX1514
FUNCTION
1
REF
REF
Internal Reference. Connect a 0.22μF ceramic capacitor from REF to the analog ground plane,
which is connected to GND. External load capability is at least 100μA.
LCD Shutdown and Frequency-Select Input.
SDFR = GND, LCD shutdown, REF, buffer amplifier and the logic regulator (REG L) output stay on
2
SDFR
SDFR
SDFR = IN, 1.5MHz switching frequency
SDRF = REF, 750kHz switching frequency
SDFR = unconnected, 430kHz switching frequency
3
4
5
FBPB
OUTB
SUPB
N.C.
N.C.
N.C.
Buffer-Amplifier Noninverting Input for the MAX1513. Not internally connected for the MAX1514.
Buffer-Amplifier Output for the MAX1513. Not internally connected for the MAX1514.
Buffer-Amplifier Supply Input for the MAX1513. Bypass to GND with a 0.1μF capacitor. Not internally
connected for the MAX1514.
Gate-Off Linear Regulator (REG N) Feedback Input. FBN regulates to 125mV nominal. Connect to
6
FBN
FBN
the center tap of a resistive voltage-divider between the REG N output and the reference voltage
(REF) to set the output voltage. Place the resistive-divider close to this pin.
7
DEL
DEL
Delay-Control Timing Capacitor. Connect a capacitor from DEL to GND to set the gate-on linear-
regulator startup delay. See the Power-Up Sequence and Delay Control Block section.
8
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