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参数资料
| 型号： | MAX1531ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/33页 |
| 文件大小： | 0K |
| 描述： | IC PS CTRLR MULTI-OUTPUT 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 五路电源监控器 |
| 电源电压： | 4.5 V ~ 28 V |
| 电流 - 电源： | 1.7mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Multiple-Output Power-Supply
Controllers for LCD Monitors
Typical Operating Characteristics (continued)
(Circuit of Figure 1; including R5, R6, and D2; T A = +25°C, unless otherwise noted.)
0
-0.2
LR5 NORMALIZED LOAD REGULATION
1.0
0.8
LR5 NORMALIZED LINE REGULATION
20mA LOAD CURRENT
0.6
-0.4
0.4
-0.6
0.2
-0.8
-1.0
0
-0.2
0
10
20
30
40
50
-25
-21
-17
-13
-9
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
Pin Description
MAX1530
PIN
MAX1531
NAME
FUNCTION
Gamma Linear Regulator (LR2) Base Drive. Open drain of an internal N-channel MOSFET.
1
1
DRV2
Connect DRV2 to the base of an external PNP pass transistor to form a positive linear
regulator. (See the Pass Transistor Selection section.)
Gamma Linear Regulator (LR2) Feedback Input. FBL2 regulates at 1.245V nominal.
2
2
FBL2
Connect FBL2 to the center tap of a resistive voltage-divider between the LR2 output and
AGND to set the output voltage. Place the divider close to the FBL2 pin.
Gate-On Linear Regulator (LR3) Feedback Input. FBL3 regulates at 1.245V nominal.
3
3
FBL3
Connect FBL3 to the center tap of a resistive voltage-divider between the LR3 output and
AGND to set the output voltage. Place the divider close to the FBL3 pin.
Gate-On Linear Regulator (LR3) Base Drive. Open drain of an internal N-channel MOSFET.
4
4
DRV3
Connect DRV3 to the base of an external PNP pass transistor to form a positive linear
regulator. (See the Pass Transistor Selection section.)
5–10, 18, 19
—
N. C.
No Connection. Not internally connected.
Adjustable Reset Input. RESET asserts low when the monitored voltage is less than the
reset trip threshold. RESET goes to a high-impedance state only after the monitored
voltage remains above the reset trip threshold for the duration of the reset timeout period.
11
11
RSTIN
Connect RSTIN to the center tap of a resistive voltage-divider between the monitored
output voltage and AGND to set the reset trip threshold. The internal RSTIN threshold of
90% of 1.238V allows direct connection of RSTIN to any of the device’s positive feedback
pins.
10
______________________________________________________________________________________
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