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| 型号： | MAX1531ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 13/33页 |
| 文件大小： | 0K |
| 描述： | IC PS CTRLR MULTI-OUTPUT 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 五路电源监控器 |
| 电源电压： | 4.5 V ~ 28 V |
| 电流 - 电源： | 1.7mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Multiple-Output Power-Supply Controllers for
LCD Monitors
Pin Description (continued)
MAX1530
PIN
MAX1531
NAME
FUNCTION
Source Drive Linear Regulator (LR4) Feedback Input. FBL4 regulates at 1.245V nominal.
—
7
FBL4
Connect FBL4 to the center tap of a resistive voltage-divider between the LR4 output and
AGND to set the output voltage. Place the divider close to the FBL4 pin.
Source Drive Linear Regulator (LR4) Base Drive. Open drain of an internal N-channel
—
8
DRV4
MOSFET. Connect DRV4 to the base of an external PNP pass transistor to form a positive
linear regulator. (See the Pass Transistor Selection section.)
Gate-Off Linear Regulator (LR5) Feedback Input. FBL5 regulates at 125mV nominal.
—
9
FBL5
Connect FBL5 to the center tap of a resistive voltage-divider between the LR5 output and
the internal 5V linear regulator output (VL) to set the output voltage. Place the divider close
to the FBL5 pin.
Gate-Off Linear Regulator (LR5) Base Drive. Open drain of an internal P-channel MOSFET.
—
10
DRV5
Connect DRV5 to the base of an external NPN pass transistor to form a negative linear
voltage regulator. (See the Pass Transistor Selection section.)
Source Drive Linear Regulator (LR4) Enable Input. When EN is above its enable threshold,
VL is above its UVLO threshold, and ONL4 is greater than the internal reference, LR4 is
enabled. Drive ONL4 with a logic signal or, for automatic sequencing, connect a capacitor
—
18
ONL4
from ONL4 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2μA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
Gate-Off Linear Regulator (LR5) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL5 is greater than the internal reference, LR5 is
enabled. Drive ONL5 with a logic signal or, for automatic sequencing, connect a capacitor
—
19
ONL5
from ONL5 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2μA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
—
—
EP
Exposed Paddle. Internally connected to GND. Connect EP to a large ground plane to
improve thermal dissipation. Do not use as the main ground connection of the IC.
______________________________________________________________________________________
13
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