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| 型号： | MAX1531ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/33页 |
| 文件大小： | 0K |
| 描述： | IC PS CTRLR MULTI-OUTPUT 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 五路电源监控器 |
| 电源电压： | 4.5 V ~ 28 V |
| 电流 - 电源： | 1.7mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Multiple-Output Power-Supply Controllers for
LCD Monitors
Pin Description (continued)
MAX1530
PIN
MAX1531
NAME
FUNCTION
Open-Drain Reset Output. RESET asserts low when the monitored voltage is less than the
reset trip threshold. RESET goes to a high-impedance state only after the monitored
12
12
RESET
voltage remains above the reset trip threshold for the duration of the reset timeout period.
RESET also asserts low when VL is less than the VL undervoltage lockout threshold, EN is
low, or the thermal, overcurrent or undervoltage fault latches are set.
Step-Down Regulator Compensation Input. A pole-zero pair must be added to
13
13
COMP
compensate the control loop by connecting a series resistor and capacitor from COMP to
AGND. (See the Compensation Design section.)
Step-Down Regulator Feedback Input. FB regulates at 1.238V nominal. Connect FB to the
14
14
FB
center tap of a resistive voltage-divider between the step-down regulator output and
AGND to set the output voltage. Place the divider close to the FB pin.
Step-Down Regulator Current-Limit Control Input. Connect this dual-mode input to VL to
set the current-limit threshold to its default value of 250mV. The overcurrent comparator
compares the voltage across the low-side N-channel MOSFET with the current-limit
15
15
ILIM
threshold. Connect ILIM to the center tap of a resistive voltage-divider between VL and
AGND to adjust the current-limit threshold to other values. In adjustable mode, the actual
current-limit threshold is 1/5th of the voltage at ILIM over a 0.25V to 3.0V range. The dual-
mode threshold for switchover to the 250mV default value is approximately 3.5V.
Gamma Linear Regulator (LR2) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL2 is greater than the internal reference, LR2 is
enabled. Drive ONL2 with a logic signal or, for automatic sequencing, connect a capacitor
16
16
ONL2
from ONL2 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2μA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
Gate-On Linear Regulator (LR3) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL3 is greater than the internal reference, LR3 is
enabled. Drive ONL3 with a logic signal or, for automatic sequencing, connect a capacitor
17
17
ONL3
from ONL3 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2μA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
20
20
PGND
Power Ground
Low-Side Gate Driver Output. DL drives the synchronous rectifier of the step-down
21
21
DL
regulator. DL swings from PGND to VL. DL remains low until VL rises above the UVLO
threshold.
Step-Down Regulator Current-Sense Input. The IC’s current-sense amplifier inputs for
22
22
LX
current-mode control connect to IN and LX. Connect IN and LX directly to the high-side N-
channel MOSFET drain and source, respectively. The low-side current-limit comparator
inputs connect to LX and PGND to sense voltage across a low-side N-channel MOSFET.
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