参数资料
型号: MAX1567ETL+
厂商: Maxim Integrated Products
文件页数: 25/35页
文件大小: 0K
描述: IC DGTL CAM PWR-SUP 6CH 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: 控制器,数字式相机
输入电压: 0.7 V ~ 5.5 V
输出数: 7
输出电压: 1.25 V ~ 5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
Six-Channel, High-Efficiency, Digital
Camera Power Supplies
TO
V BATT
MAX1566
MAX1567
(PARTIAL)
PVSU
15V
AUX1
PWM
DL1
D6
100mA
FB1
AUX1OK
PV
PVSU
TO
V BATT
GATED +5V
TO CCD
V SU
+5V
CURRENT-
MODE
LXSU
L2
STEP-UP
PWM
PGSU
FBSU
Figure 16. AUX1OK Drives an External PFET that Gates 5V Supply to the CCD After the +15V CCD Bias Supply Is Up
Soft-Start
The MAX1566/MAX1567 channels feature a soft-start
function that limits inrush current and prevents exces-
sive battery loading at startup by ramping the output
voltage of each channel up to the regulation voltage.
This is accomplished by ramping the internal reference
inputs to each channel error amplifier from 0V to the
1.25V reference voltage over a period of 4096 oscillator
cycles (16ms at 500kHz) when initial power is applied
or when a channel is enabled.
The step-down soft-start ramp takes half the time (2048
clock cycles) of the other channel ramps. This allows
the step-down and main outputs to track each other
and rise at nearly the same dV/dt rate on power-up.
Once the step-down output reaches its regulation point
(1.5V or 1.8V typ), the main output (3.3V typ) continues
to rise at the same ramp rate. See the Typical
Operating Characteristics Main and Step-Down Startup
Waveforms graphs.
Soft-start is not included in the step-up converter to
avoid limiting startup capability with loading.
Fault Protection
The MAX1566/MAX1567 have robust fault and overload
protection. After power-up, the device is set to detect
an out-of-regulation state that could be caused by an
overload or short. If any DC-to-DC converter channel
(step-up, main, step-down, or any of the auxiliary con-
trollers) remains faulted for 100,000 clock cycles
(200ms at 500kHz), then all outputs latch off until the
step-up DC-to-DC converter is reinitialized by the
ONSU pin or by cycling the input power. The fault-
detection circuitry for any channel is disabled during its
initial turn-on soft-start sequence.
An exception to the standard fault behavior is that there
is no 100,000 clock cycle delay in entering the fault
state if the step-up output (PVSU) is dragged below its
2.5V UVLO threshold or is shorted. In this case, the
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