参数资料
型号: MAX1567ETL+
厂商: Maxim Integrated Products
文件页数: 27/35页
文件大小: 0K
描述: IC DGTL CAM PWR-SUP 6CH 40TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: 控制器,数字式相机
输入电压: 0.7 V ~ 5.5 V
输出数: 7
输出电压: 1.25 V ~ 5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
Six-Channel, High-Efficiency, Digital
Camera Power Supplies
up may have difficulty starting into heavy loads (see the
Minimum Startup Voltage vs. Load Current (OUTSU)
graph in the Typical Operating Characteristics ); however,
this can be remedied by connecting an external P-
channel load switch driven by SCF so the load is not
connected until the PVSU is in regulation (Figure 17).
Shutdown
The step-up converter is activated with a high input at
ONSU. The main converter (step-up or step-down) is acti-
vated by a high input on ONM. The step-down and auxil-
iary DC-to-DC converters 1, 2, and 3 activate with high
inputs at ONSD, ON1, ON2, and ON3, respectively. The
step-down, main, and AUX_ converters cannot be activat-
ed until PVSU is in regulation. For automatic startup, con-
nect ON_ to PVSU or a logic level greater than 1.6V.
Design Procedure
Setting the Switching Frequency
Choose a switching frequency to optimize external
component size or circuit efficiency for the particular
application. Typically, switching frequencies between
400kHz and 500kHz offer a good balance between
component size and circuit efficiency—higher frequen-
cies generally allow smaller components, and lower fre-
quencies give better conversion efficiency. The
switching frequency is set with an external timing resis-
tor (R OSC ) and capacitor (C OSC ). At the beginning of a
cycle, the timing capacitor charges through the resistor
until it reaches V REF . The charge time, t 1 , is as follows:
t 1 = -R OSC x (C OSC + C par ) x ln (1 - 1.25 / V PVSU )
where C par (15pF typ) is the parasitic capacitance at
the OSC pin due to internal ESD protection structure
and the die-to-package capacitance.
The internal comparator that compares the capacitor
C OSC voltage to the reference has a delay t d of 50ns
(typ). The capacitor voltage then decays to zero over
time, t 2 = 200ns. The oscillator frequency is as follows:
f OSC = 1 / (t 1 + t d + t 2 )
f OSC can be set from 100kHz to 1MHz. Choose C OSC
between 22pF and 470pF. Determine R OSC :
R OSC = (200ns + 50ns - 1/ f OSC ) /
([C OSC + C par ] ln[1 - 1.25 / V PVSU ])
See the Typical Operating Characteristics for f OSC vs.
R OSC using different values of C OSC .
Setting Output Voltages
All MAX1566/MAX1567 output voltages are resistor set.
The FB_ threshold is 1.25V for all channels except for
FB3L (0.2V) on both devices and FB2 (inverter) on the
MAX1567. When setting the voltage for any channel
except the MAX1567 AUX2, connect a resistive volt-
age-divider from the channel output to the correspond-
ing FB_ input and then to GND. The FB_ input bias
current is less than 100nA, so choose the bottom-side
(FB_-to-GND) resistor to be 100k ? or less. Then calcu-
late the top-side (output-to-FB_) resistor:
R TOP = R BOTTOM [(V OUT / 1.25) - 1]
When using AUX3 to drive white LEDs (Figure 7), select
the LED current-setting resistor (R3, Figure 7) using the
following formula:
R3 = 0.2V / I LED
The FB2 threshold on the MAX1567 is 0V. To set the
AUX2 negative output voltage, connect a resistive volt-
age-divider from the negative output to the FB2 input,
and then to REF. The FB2 input bias current is less than
100nA, so choose the REF-side (FB2-to-REF) resistor
(R REF ) to be 100k ? or less. Then calculate the top-side
(output-to-FB2) resistor:
R TOP = R REF (-V OUT(AUX2) / 1.25)
General Filter Capacitor Selection
The input capacitor in a DC-to-DC converter reduces
current peaks drawn from the battery or other input
power source and reduces switching noise in the con-
troller. The impedance of the input capacitor at the
switching frequency should be less than that of the
input source so high-frequency switching currents do
not pass through the input source.
The output capacitor keeps output ripple small and
ensures control-loop stability. The output capacitor must
also have low impedance at the switching frequency.
Ceramic, polymer, and tantalum capacitors are suitable,
with ceramic exhibiting the lowest ESR and high-frequen-
cy impedance.
Output ripple with a ceramic output capacitor is
approximately as follows:
V RIPPLE = I L(PEAK) [1 / (2 π x f OSC x C OUT )]
If the capacitor has significant ESR, the output ripple
component due to capacitor ESR is as follows:
V RIPPLE(ESR) = I L(PEAK) x ESR
Output capacitor specifics are also discussed in each
converter’s Compensation section.
Step-Up Component Selection
This section describes component selection for the
step-up, as well as for the main, if SUSD = PV.
The external components required for the step-up are
an inductor, an input and output filter capacitor, and a
compensation RC.
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27
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