- 您现在的位置：买卖IC网 > PDF目录16795 > MAX16066ETL+ (Maxim Integrated Products)IC SYSTEM MANAGER 8CH 40-TQFN PDF资料下载
参数资料
| 型号： | MAX16066ETL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 44/62页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 8CH 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 应用： | 电源监控器，序列发生器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 4.5mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The block write procedure is the following:
the configuration register or configuration flash or FFh
1)
2)
3)
4)
5)
6)
7)
8)
9)
The master sends a START condition.
The master sends the 7-bit slave address and a
write bit (low).
The addressed slave asserts an ACK on SDA.
The master sends the 8-bit command code for a
block write (A5h).
The addressed slave asserts an ACK on SDA.
The master sends the 8-bit byte count (1 byte to 16
bytes), n.
The addressed slave asserts an ACK on SDA.
The master sends 8 bits of data.
The addressed slave asserts an ACK on SDA.
in user flash, the address pointer stays at 8Fh or FFh,
respectively. The block read procedure is the following:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a write
bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends 8 bits of the block read command (A6h).
5) The slave asserts an ACK on SDA, unless busy.
6) The master generates a REPEATED START condition.
7) The master sends the 7-bit slave address and a read
bit (high).
8) The slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 n - 1 times.
11) The master sends a STOP condition.
When PEC is enabled, the Block Write protocol becomes:
9) The slave sends the 8-bit byte count (16).
10) The master asserts an ACK on SDA.
11) The slave sends 8 bits of data.
1)
2)
3)
4)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
The addressed slave asserts an ACK on the data line.
The master sends 8 bits of the block write command code.
12) The master asserts an ACK on SDA.
13) Repeat steps 11 and 12 up to fifteen times.
14) The master asserts a NACK on SDA.
15) The master sends a STOP condition.
When PEC is enabled, the Block Read protocol becomes:
5)
6)
7)
8)
9)
The slave asserts an ACK on the data line.
The master sends an 8-bit byte count (min 1, max
16), n.
The slave asserts an ACK on the data line.
The master sends 8 bits of data.
The slave asserts an ACK on the data line.
1)
2)
3)
4)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
The addressed slave asserts an ACK on the data line.
The master sends 8 bits of the block read command
code.
10) Repeat 8 and 9 n - 1 times.
11) The master sends an 8-bit PEC byte.
12) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
13) The master generates a STOP condition.
Block Read
The block read protocol (see Figure 14) allows the
master device to read a block of up to 16 bytes from
memory. Read fewer than 16 bytes of data by issuing
an early STOP condition from the master, or by generat-
ing a NACK with the master. The destination address
should be preloaded by a previous send byte command;
otherwise the block read command begins to read at
the current address pointer. If the number of bytes to
be read causes the address pointer to exceed 8Fh for
5) The slave asserts an ACK on the data line unless
busy.
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave ID plus a read
bit (high).
8) The slave asserts an ACK on the data line.
9) The slave sends an 8-bit byte count (16).
10) The master asserts an ACK on the data line.
11) The slave sends 8 bits of data.
12) The master asserts an ACK on the data line.
13) Repeat 11 and 12 up to 15 times.
14) The slave sends an 8-bit PEC byte.
15) The master asserts a NACK on the data line.
16) The master generates a STOP condition.
44
_____________________________________________________________________________________
相关PDF资料 |
PDF描述 |
|---|---|
| H3BBS-1006M | IDC CABLE - HSR10S/AE10M/HSR10S |
| MAX16067ETJ+ | IC SYSTEM MANAGER 6CH 32-TQFN |
| RCM06DTKT-S288 | CONN EDGECARD 12POS .156 EXTEND |
| H3AAH-1606G | IDC CABLE - HSC16H/AE16G/HSC16H |
| V300C12E150BF | CONVERTER MOD DC/DC 12V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX16066ETL+ | 功能描述:监控电路 8Ch Power Supply Sequencer RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16066ETL+T | 功能描述:监控电路 8Ch Power Supply Sequencer RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16067ETJ+ | 功能描述:监控电路 6Ch System Manager RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16067ETJ+T | 功能描述:监控电路 6Ch System Manager RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16067EVKIT+ | 功能描述:监控电路 6-Channel System Manager RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。